{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,29]],"date-time":"2026-03-29T16:28:50Z","timestamp":1774801730601,"version":"3.50.1"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/iccd.2008.4751864","type":"proceedings-article","created":{"date-parts":[[2009,1,20]],"date-time":"2009-01-20T20:27:15Z","timestamp":1232483235000},"page":"212-218","source":"Crossref","is-referenced-by-count":61,"title":["Test-access mechanism optimization for core-based three-dimensional SOCs"],"prefix":"10.1109","author":[{"given":"Xiaoxia","family":"Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yibo Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yuan Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","year":"0"},{"key":"22","author":"xpress-mp","year":"2007"},{"key":"17","year":"0"},{"key":"23","article-title":"interconnect and thermal-aware floorplanning for 3d microprocessors","author":"hung","year":"2006","journal-title":"ISQED"},{"key":"18","article-title":"scan chain design for threedimensional (3d) ics","author":"wu","year":"2007","journal-title":"ICCD"},{"key":"24","year":"0"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"16","article-title":"the long road to 3-d integration: are we there yet?","author":"vucurevich","year":"2007","journal-title":"Keynote speech at the 3D Architecture Conference"},{"key":"13","year":"0"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996687"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1007\/BF02579324"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1252857"},{"key":"21","author":"bertsimas","year":"1997","journal-title":"Introduction to Linear Optimization"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045019"},{"key":"20","author":"gary","year":"1979","journal-title":"Computers and Intractability A Guide to the Theory of NP-Completeness"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/2.769444"},{"key":"10","year":"0"},{"key":"7","author":"weerasekera","year":"2007","journal-title":"Extending systems-on-chip to the third dimension Performance cost and technological tradeoffs"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/5.929647"},{"key":"5","year":"0"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826560"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"}],"event":{"name":"2008 IEEE International Conference on Computer Design (ICCD)","location":"Lake Tahoe, CA, USA","start":{"date-parts":[[2008,10,12]]},"end":{"date-parts":[[2008,10,15]]}},"container-title":["2008 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4740204\/4751825\/04751864.pdf?arnumber=4751864","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T19:23:48Z","timestamp":1489778628000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4751864\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/iccd.2008.4751864","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}