{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:44:33Z","timestamp":1725615873858},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/iccd.2008.4751909","type":"proceedings-article","created":{"date-parts":[[2009,1,20]],"date-time":"2009-01-20T15:27:15Z","timestamp":1232465235000},"page":"514-519","source":"Crossref","is-referenced-by-count":2,"title":["Techniques for increasing effective data bandwidth"],"prefix":"10.1109","author":[{"given":"Christopher","family":"Nitta","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matthew","family":"Farrens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1016\/j.cad.2004.09.015"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DCC.2006.35"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TVCG.2006.143"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/1054943.1054945"},{"key":"13","first-page":"59","article-title":"compressibility characteristics of address\/data transfers in commercial workloads","author":"kant","year":"2002","journal-title":"Proc of the Fifth Workshop on Computer Architecture Evaluation Using Commercial Workloads"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/378993.379235"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.4"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346200"},{"journal-title":"Pentium Processor","year":"1997","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/40.641597"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2001.903253"},{"key":"7","doi-asserted-by":"crossref","first-page":"128","DOI":"10.1145\/115953.115966","article-title":"dynamic base register caching: a technique for reducing address bus width","author":"farrens","year":"1991","journal-title":"The 16th Annual International Symposium on Computer Architecture"},{"year":"0","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TADVP.2004.830355"},{"journal-title":"Intel\ufffd Core?2 Extreme Processor QX9000? Series and Intel\ufffdCore?2 Quad Processor Q9000? Series Datasheet","year":"2008","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/EURMIC.1996.546466"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.1995.386552"}],"event":{"name":"2008 IEEE International Conference on Computer Design (ICCD)","start":{"date-parts":[[2008,10,12]]},"location":"Lake Tahoe, CA, USA","end":{"date-parts":[[2008,10,15]]}},"container-title":["2008 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4740204\/4751825\/04751909.pdf?arnumber=4751909","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T11:56:30Z","timestamp":1497786990000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4751909\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/iccd.2008.4751909","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}