{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:47:34Z","timestamp":1776955654539,"version":"3.51.4"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/iccd.2008.4751913","type":"proceedings-article","created":{"date-parts":[[2009,1,20]],"date-time":"2009-01-20T20:27:15Z","timestamp":1232483235000},"page":"538-543","source":"Crossref","is-referenced-by-count":4,"title":["A dynamic accuracy-refinement approach to timing-driven technology mapping"],"prefix":"10.1109","author":[{"given":"Sz-Cheng","family":"Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie-Hong R.","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"17","first-page":"383","article-title":"an integrated technology mapping environment","author":"mishchenko","year":"2005","journal-title":"Proc IWLS"},{"key":"15","year":"0"},{"key":"16","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1016\/S0167-9260(99)00023-1"},{"key":"14","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/FPGA.1995.242045","article-title":"on nominal delay minimization in lut-based fpga technology mapping","author":"cong","year":"1995","journal-title":"Third International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"11","doi-asserted-by":"crossref","first-page":"348","DOI":"10.1145\/277044.277142","article-title":"Delay-optimal technology mapping by DAG covering","author":"kukimoto","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1999.761178"},{"key":"3","first-page":"121","article-title":"placement-driven technology mapping for lut-based fpgas","author":"lin","year":"2003","journal-title":"Proc FPGA"},{"key":"2","first-page":"177","article-title":"integrating logic synthesis, technology mapping, and retiming","author":"mishchenko","year":"2005","journal-title":"Proc IWLS"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/43.644605"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"7","first-page":"341","article-title":"dagon: technology binding and local optimization by dag matching","author":"keutzer","year":"1987","journal-title":"Proc DAC"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344680"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055166"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809646"},{"key":"9","first-page":"79","article-title":"performanceoriented technology mapping","author":"touati","year":"1990","journal-title":"Proc 6th MIT Conf on Advanced Research in VLSI"},{"key":"8","article-title":"logic synthesis for vlsi design","author":"rudell","year":"1989"}],"event":{"name":"2008 IEEE International Conference on Computer Design (ICCD)","location":"Lake Tahoe, CA, USA","start":{"date-parts":[[2008,10,12]]},"end":{"date-parts":[[2008,10,15]]}},"container-title":["2008 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4740204\/4751825\/04751913.pdf?arnumber=4751913","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T15:56:32Z","timestamp":1497801392000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4751913\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iccd.2008.4751913","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}