{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:57:37Z","timestamp":1761580657000,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,10]]},"DOI":"10.1109\/iccd.2008.4751930","type":"proceedings-article","created":{"date-parts":[[2009,1,20]],"date-time":"2009-01-20T20:27:15Z","timestamp":1232483235000},"page":"652-657","source":"Crossref","is-referenced-by-count":22,"title":["ECO-Map: Technology remapping for post-mask ECO using simulated annealing"],"prefix":"10.1109","author":[{"given":"Nilesh A.","family":"Modi","sequence":"first","affiliation":[]},{"given":"Malgorzata","family":"Marek-Sadowska","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/43.784122"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810642"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981075"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357977"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.836733"},{"key":"13","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1109\/TC.1968.229394","article-title":"fault testing and diagnosis in combinational digital circuits","volume":"c 17","author":"kautz","year":"1968","journal-title":"IEEE Transactions on Computers"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310007"},{"key":"11","doi-asserted-by":"crossref","first-page":"503","DOI":"10.1145\/157485.165003","article-title":"diagnosis and correction of logic design errors in digital circuits","author":"chung","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"12","doi-asserted-by":"crossref","first-page":"212","DOI":"10.1145\/196244.196356","article-title":"rectification of multiple logic design errors in multiple output circuits","author":"tomita","year":"1994","journal-title":"31st Design Automation Conference"},{"key":"21","first-page":"91","article-title":"automating post-silicon debugging and repair","author":"chang","year":"0","journal-title":"ICC '07"},{"key":"20","first-page":"530","article-title":"eco timing optimization using spare cells","author":"chen","year":"0","journal-title":"ICC '07"},{"key":"22","first-page":"544","article-title":"engineering change using spare cells with constant insertion","author":"kuo","year":"0","journal-title":"ICC '07"},{"year":"0","key":"23"},{"key":"24","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1697-8","author":"sechen","year":"1988","journal-title":"VLSI Placement and Global Routing Using Simulated Annealing"},{"key":"25","article-title":"integrated logic synthesis using simulated annealing","author":"kuehlmann","year":"0","journal-title":"IWLS 2006"},{"key":"26","article-title":"a scalable and accurate rectilinear steiner minimal tree algorithm","author":"wong","year":"2008","journal-title":"VLSI Design Automation and Test"},{"key":"27","article-title":"sis: a system for sequential circuit synthesis","author":"sentovich","year":"1992","journal-title":"UCB\/ERLM92\/41"},{"key":"28","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-1627-5","author":"otten","year":"1989","journal-title":"The Annealing Algorithm"},{"key":"29","first-page":"177","article-title":"timing-driven placement using design hierarchy guided constraint generation","author":"yang","year":"0","journal-title":"ICCAD '02"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1117\/1.1668275"},{"journal-title":"On-Chip System integration Solving Technology and Commercial Issues","year":"0","author":"tanaka","key":"2"},{"key":"10","first-page":"632","article-title":"a redesign technique for combinational circuits based on gate reconnections","author":"kukimoto","year":"0","journal-title":"ICC 94"},{"journal-title":"Edition","year":"2005","key":"1"},{"key":"7","first-page":"451","article-title":"engineering change in a non-deterministic fsm setting","author":"khatri","year":"0","journal-title":"DAC 1996"},{"key":"6","first-page":"391","article-title":"incremental logic synthesis through gate logic structure identification","author":"shinsha","year":"0","journal-title":"DAC 1986"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353654"},{"year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217604"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896480"}],"event":{"name":"2008 IEEE International Conference on Computer Design (ICCD)","start":{"date-parts":[[2008,10,12]]},"location":"Lake Tahoe, CA, USA","end":{"date-parts":[[2008,10,15]]}},"container-title":["2008 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4740204\/4751825\/04751930.pdf?arnumber=4751930","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T15:56:32Z","timestamp":1497801392000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4751930\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/iccd.2008.4751930","relation":{},"subject":[],"published":{"date-parts":[[2008,10]]}}}