{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,12]],"date-time":"2025-12-12T13:19:52Z","timestamp":1765545592385,"version":"3.28.0"},"reference-count":36,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,10]]},"DOI":"10.1109\/iccd.2009.5413115","type":"proceedings-article","created":{"date-parts":[[2010,2,17]],"date-time":"2010-02-17T18:35:32Z","timestamp":1266431732000},"page":"472-478","source":"Crossref","is-referenced-by-count":19,"title":["The impact of liquid cooling on 3D multi-core processors"],"prefix":"10.1109","author":[{"given":"Hyung Beom","family":"Jang","sequence":"first","affiliation":[]},{"given":"Ikroh","family":"Yoon","sequence":"additional","affiliation":[]},{"given":"Cheol Hong","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Seungwon","family":"Shin","sequence":"additional","affiliation":[]},{"given":"Sung Woo","family":"Chung","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Perfmon2 patch","year":"0","key":"ref33"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243773"},{"key":"ref30","first-page":"519","article-title":"Three-Dimensional Cache Design Exploration Using 3D Cacti","author":"tsai","year":"2005","journal-title":"Proc of IEEE Int Conf on Computer Design"},{"year":"2002","key":"ref36","article-title":"Berkeley Predictive Technology Model (BPTM)"},{"journal-title":"User's guide Icepak 4 4 6","year":"2007","key":"ref35"},{"journal-title":"Standard Performance Evaluation Corporation","year":"0","key":"ref34"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329460"},{"key":"ref11","first-page":"727","article-title":"Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs","author":"im","year":"2000","journal-title":"Technical Digest International Electron Devices Meeting"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253186"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.08.0208.0052"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TDSC.2009.16"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1115\/1.1839582"},{"key":"ref16","article-title":"Temperature and Supply Voltage Aware Performance and Power Modeling at Microarchitecture","volume":"24","author":"liao","year":"2005","journal-title":"IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1366230.1366261"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.59"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/EPTC.2002.1185702"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ITHERM.2008.4544386"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120787"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310781"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981091"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/988952.989034"},{"key":"ref2","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.1257591"},{"key":"ref20","first-page":"991","article-title":"A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy","author":"loi","year":"2006","journal-title":"Proc 43rd ACM\/IEEE Design Automation Conf"},{"key":"ref22","first-page":"525","article-title":"Implemeting Caches in a 3D Technology for High Performance Processors","author":"puttaswamy","year":"2005","journal-title":"Proc of the Int Conf on Comp Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1127908.1127946"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346197"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693742"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996687"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2005.1502578"}],"event":{"name":"2009 IEEE International Conference on Computer Design (ICCD 2009)","start":{"date-parts":[[2009,10,4]]},"location":"Lake Tahoe, CA, USA","end":{"date-parts":[[2009,10,7]]}},"container-title":["2009 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5406656\/5413104\/05413115.pdf?arnumber=5413115","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T04:29:00Z","timestamp":1489897740000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5413115\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,10]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/iccd.2009.5413115","relation":{},"subject":[],"published":{"date-parts":[[2009,10]]}}}