{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T05:40:41Z","timestamp":1740807641362,"version":"3.38.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,10]]},"DOI":"10.1109\/iccd.2010.5647634","type":"proceedings-article","created":{"date-parts":[[2010,12,9]],"date-time":"2010-12-09T15:42:09Z","timestamp":1291909329000},"page":"509-514","source":"Crossref","is-referenced-by-count":0,"title":["Inter-socket victim cacheing for platform power reduction"],"prefix":"10.1109","author":[{"given":"Subhra","family":"Mazumdar","sequence":"first","affiliation":[]},{"given":"Dean M.","family":"Tullsen","sequence":"additional","affiliation":[]},{"given":"Justin","family":"Song","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","article-title":"Cacti 5.1","author":"thoziyoor","year":"2008","journal-title":"HP Laboratories Tech Rep"},{"doi-asserted-by":"publisher","key":"14","DOI":"10.1145\/605397.605403"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1145\/383082.383118"},{"key":"12","doi-asserted-by":"crossref","first-page":"392","DOI":"10.1109\/ISCA.1995.524578","article-title":"Simultaneous multithreading: Maximizing on-chip parallelism","author":"tullsen","year":"1995","journal-title":"Proceedings 22nd Annual International Symposium on Computer Architecture ISCA"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1145\/378993.379007"},{"key":"2","article-title":"Performance evaluation of virtualization technologies for server consolidation","author":"padala","year":"2007","journal-title":"HP Laboratories Tech Rep"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/MC.2007.443"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1145\/871506.871571"},{"key":"7","doi-asserted-by":"crossref","DOI":"10.1145\/1150019.1136509","article-title":"Cooperative cacheing for chip multiprocessors","author":"chang","year":"2006","journal-title":"Proceedings of the 20th Annual International Symposium on Computer Architecture"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/ISCA.1990.134547"},{"key":"5","article-title":"Design and implementation of power aware virtual memory","author":"huang","year":"2003","journal-title":"USENIX Annual Technical Conference"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/DAC.2002.1012714"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1007\/978-3-540-30121-9_1"},{"key":"8","doi-asserted-by":"crossref","DOI":"10.1145\/224056.224072","article-title":"Implementing global memory management in a workstation cluster","author":"feeley","year":"1995","journal-title":"Proceedings of the fifteenth ACM symposium on Operating systems principles"}],"event":{"name":"2010 IEEE International Conference on Computer Design (ICCD 2010)","start":{"date-parts":[[2010,10,3]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2010,10,6]]}},"container-title":["2010 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5640356\/5647518\/05647634.pdf?arnumber=5647634","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,28]],"date-time":"2025-02-28T16:18:48Z","timestamp":1740759528000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5647634\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iccd.2010.5647634","relation":{},"subject":[],"published":{"date-parts":[[2010,10]]}}}