{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T21:09:39Z","timestamp":1725656979407},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,10]]},"DOI":"10.1109\/iccd.2010.5647702","type":"proceedings-article","created":{"date-parts":[[2010,12,9]],"date-time":"2010-12-09T15:42:09Z","timestamp":1291909329000},"page":"356-363","source":"Crossref","is-referenced-by-count":3,"title":["Optimal power\/performance pipelining for error resilient processors"],"prefix":"10.1109","author":[{"given":"Nicolas","family":"Zea","sequence":"first","affiliation":[]},{"given":"John","family":"Sartori","sequence":"additional","affiliation":[]},{"given":"Ben","family":"Ahrens","sequence":"additional","affiliation":[]},{"given":"Rakesh","family":"Kumar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"SPEC CPU2000","year":"2000","key":"17"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"key":"15","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"journal-title":"The SMTSIM Multithreading simulator","year":"2010","author":"tullsen","key":"16"},{"journal-title":"A Unified Model for Timing Speculation Evaluating the Impact of Technology Scaling Cmos Design Style and Fault Recovery Mechanism","year":"2010","author":"de kruijf","key":"13"},{"journal-title":"Cmos Process Variations A Critical Operation Point Hypothesis","year":"2008","author":"patel","key":"14"},{"key":"11","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1109\/ISCA.2002.1003558","article-title":"The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays","author":"hrishikesh","year":"2002","journal-title":"ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2002.1176261"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419690"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798256"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393383"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.42"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/313817.313834"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837481"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2010.5416652"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566437"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253188"}],"event":{"name":"2010 IEEE International Conference on Computer Design (ICCD 2010)","start":{"date-parts":[[2010,10,3]]},"location":"Amsterdam, Netherlands","end":{"date-parts":[[2010,10,6]]}},"container-title":["2010 IEEE International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5640356\/5647518\/05647702.pdf?arnumber=5647702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,4]],"date-time":"2023-06-04T12:33:37Z","timestamp":1685882017000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5647702\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,10]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/iccd.2010.5647702","relation":{},"subject":[],"published":{"date-parts":[[2010,10]]}}}