{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T12:19:21Z","timestamp":1725711561805},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/iccd.2011.6081419","type":"proceedings-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T21:47:00Z","timestamp":1321912020000},"page":"326-331","source":"Crossref","is-referenced-by-count":15,"title":["Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology"],"prefix":"10.1109","author":[{"given":"Farshad","family":"Moradi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgios","family":"Panagopoulos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georgios","family":"Karakonstantis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dag","family":"Wisland","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Mahmoodi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jens Kargaard","family":"Madsen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"158","article-title":"A 45nm 0.6V cross-point 8T SRAM with negative biased read\/write assist","author":"yabuuchi","year":"2009","journal-title":"VLSI Circuits Symposium"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2029114"},{"key":"ref12","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 0.179J.µm2 cell in 40nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"0","journal-title":"ISSCC 2009"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2084490"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052598"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1196114"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2010818"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001941"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.604077"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908005"},{"key":"ref5","first-page":"328","article-title":"A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy","author":"verma","year":"2007","journal-title":"IEEE ISSCC"},{"key":"ref8","first-page":"212","article-title":"A 45-nm single-port and dual-port SRAM family with robust read\/write stabilizing circuitry under DVFS environment","author":"nii","year":"2008","journal-title":"VLSI Circuits Symposium"},{"key":"ref7","first-page":"458","article-title":"A process-variation-tolerant dual-power-supply SRAM with 0.179J.µm2 Cell in 40nm CMOS using level-programmable wordline driver","author":"hirabayashi","year":"2009","journal-title":"IEEE ISSCC 2009"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2010.2093140"},{"key":"ref9","first-page":"326","article-title":"A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations","author":"yabuuchi","year":"2007","journal-title":"IEEE ISSCC 2000"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.1995.499247"}],"event":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD 2011)","start":{"date-parts":[[2011,10,9]]},"location":"Amherst, MA, USA","end":{"date-parts":[[2011,10,12]]}},"container-title":["2011 IEEE 29th International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6066261\/6081363\/06081419.pdf?arnumber=6081419","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T17:07:17Z","timestamp":1490116037000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081419\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iccd.2011.6081419","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}