{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:15Z","timestamp":1763468055570,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/iccd.2011.6081425","type":"proceedings-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T16:47:00Z","timestamp":1321894020000},"page":"366-372","source":"Crossref","is-referenced-by-count":9,"title":["Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory"],"prefix":"10.1109","author":[{"given":"Guangyu","family":"Sun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Eren","family":"Kursun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jude A.","family":"Rivers","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1109\/HOTCHIPS.2010.7480057","article-title":"Status and prospect for mram technology","author":"tehrani","year":"2010"},{"key":"ref11","first-page":"1","article-title":"Using magnetic RAM to build low-power and soft error-resilient L1 cache","volume":"pp","author":"sun","year":"2010","journal-title":"IEEE Transactions on VLSI"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/BMAS.2006.283467"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/19\/16\/165209"},{"article-title":"Architecture design for soft errors","year":"2008","author":"mukherjee","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1147\/rd.501.0005"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1063\/1.2837800"},{"article-title":"Spin torque random access memory down to 22nm technology","year":"0","author":"wang","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref28","first-page":"1","article-title":"Analysis of spatial and temporal behavior of three-dimensional multi-core architectures towards run-time thermal management","author":"kursun","year":"2010","journal-title":"IEEE ITherm"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1147\/JRD.2008.5388561"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.174"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1147\/rd.523.0293"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1816012"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555771"},{"year":"2007","key":"ref9","article-title":"Document number: Brmramslscltrl-freescale mram technology"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253181"},{"key":"ref20","first-page":"991","article-title":"A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy","author":"loi","year":"2006","journal-title":"Proceedings of DAC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1147\/rd.494.0589"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1454115.1454128"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's general execution-driven multiprocessor simulator (gems) toolset","volume":"33","author":"martin","year":"2005","journal-title":"SIGARCH Comput Archit News"},{"key":"ref26","first-page":"519","article-title":"Three-Dimensional Cache Design Exploration Using 3DCacti","author":"tsai","year":"2005","journal-title":"Proceedings of ICCD"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"}],"event":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD 2011)","start":{"date-parts":[[2011,10,9]]},"location":"Amherst, MA, USA","end":{"date-parts":[[2011,10,12]]}},"container-title":["2011 IEEE 29th International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6066261\/6081363\/06081425.pdf?arnumber=6081425","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,19]],"date-time":"2019-06-19T18:38:49Z","timestamp":1560969529000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081425\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/iccd.2011.6081425","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}