{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:49:26Z","timestamp":1759146566084,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/iccd.2011.6081426","type":"proceedings-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T16:47:00Z","timestamp":1321894020000},"page":"373-380","source":"Crossref","is-referenced-by-count":18,"title":["A morphable phase change memory architecture considering frequent zero values"],"prefix":"10.1109","author":[{"given":"Mohammad","family":"Arjomand","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amin","family":"Jadidi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ali","family":"Shafiee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid","family":"Sarbazi-Azad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/PACT.2009.29"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/1555754.1555758"},{"key":"ref12","article-title":"FlexFS: a flexible flash file system for MLC NAND flash memory","author":"lee","year":"2009","journal-title":"USENIX"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1145\/1555754.1555759"},{"key":"ref14","first-page":"92","article-title":"Multifacet general execution-driven multiprocessor simulator (GEMS) toolset","volume":"33","author":"martin","year":"2005","journal-title":"CAN"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/2.982916"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1145\/378993.379235"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1145\/237090.237173"},{"year":"2010","journal-title":"CACTI An Integrated Cache and Memory Access Time Cycle Time Area Leakage and Dynamic Power Model","key":"ref4"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/ASPDAC.2011.5722186"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/1815961.1815981"},{"year":"0","journal-title":"Emerging Reaseach Device (ERD) &#x2013; Emerging Research Material (ERM) ITRS International Technology Roadmap for Semiconductor 2010 report","key":"ref5"},{"key":"ref8","article-title":"PARSEC 2.0: a new benchmark suite for chip-multiprocessors","author":"bienia","year":"2009","journal-title":"MOBS"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/JSSC.2008.2006439"},{"key":"ref2","first-page":"7","article-title":"Leveraging value locality in optimizing NAND flash-based SSDs","author":"gupta","year":"2011","journal-title":"FAST"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/ASPDAC.2011.5722206"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1145\/1669112.1669157"}],"event":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD 2011)","start":{"date-parts":[[2011,10,9]]},"location":"Amherst, MA, USA","end":{"date-parts":[[2011,10,12]]}},"container-title":["2011 IEEE 29th International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6066261\/6081363\/06081426.pdf?arnumber=6081426","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T13:11:05Z","timestamp":1490101865000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081426\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iccd.2011.6081426","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}