{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T20:55:39Z","timestamp":1725742539902},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,9]]},"DOI":"10.1109\/iccd.2012.6378615","type":"proceedings-article","created":{"date-parts":[[2012,12,18]],"date-time":"2012-12-18T21:52:22Z","timestamp":1355867542000},"page":"45-48","source":"Crossref","is-referenced-by-count":10,"title":["Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs"],"prefix":"10.1109","author":[{"given":"Matteo","family":"Dall'Osso","sequence":"first","affiliation":[]},{"given":"Gianluca","family":"Biccari","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Giovannini","sequence":"additional","affiliation":[]},{"given":"Davide","family":"Bertozzi","sequence":"additional","affiliation":[]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"0","key":"15"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253633"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/4.881217"},{"journal-title":"High Performance Communication Networks","year":"2000","author":"walrand","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.808291"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008155020711"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"journal-title":"Parallel Computer Architecture A Hardware\/Software Approach","year":"1999","author":"culler","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2002.1016885"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/43.945302"},{"key":"5","first-page":"248","article-title":"Clock rate versus IPC: the end of the road for conventional microarchitectures","author":"agarwal","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"4","first-page":"152","article-title":"Methodologies and tools for pipelined on-chip interconnect","author":"scheffer","year":"2002","journal-title":"Int Conf On Computer Design"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ARVLSI.1999.756051"},{"key":"8","first-page":"673","article-title":"MicroNetwork-based integration for sees","author":"wingard","year":"2001","journal-title":"DAC 2001"}],"event":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD 2012)","start":{"date-parts":[[2012,9,30]]},"location":"Montreal, QC, Canada","end":{"date-parts":[[2012,10,3]]}},"container-title":["2012 IEEE 30th International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6362370\/6378602\/06378615.pdf?arnumber=6378615","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T00:47:39Z","timestamp":1490143659000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6378615\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iccd.2012.6378615","relation":{},"subject":[],"published":{"date-parts":[[2012,9]]}}}