{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T05:05:03Z","timestamp":1725426303533},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/iccd.2013.6657092","type":"proceedings-article","created":{"date-parts":[[2013,11,11]],"date-time":"2013-11-11T22:22:16Z","timestamp":1384208536000},"page":"499-502","source":"Crossref","is-referenced-by-count":2,"title":["Optimizing post-silicon conformance checking"],"prefix":"10.1109","author":[{"given":"Li","family":"Lei","sequence":"first","affiliation":[]},{"given":"Kai","family":"Cong","sequence":"additional","affiliation":[]},{"given":"Fei","family":"Xie","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","article-title":"CUTE: A concolic unit testing engine for C","author":"sen","year":"0","journal-title":"Proceedings of ESEC\/FSE 2005"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1145\/1273463.1273478"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/2254064.2254088"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1065010.1065036"},{"key":"3","article-title":"BackSpace: Formal Analysis for Post-Silicon Debug","author":"de paula","year":"0","journal-title":"Proc Of FMCAD 2008"},{"key":"2","article-title":"QEMU, a fast and portable dynamic translator","author":"bellard","year":"0","journal-title":"Proc Of ATEC 2005"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488770"},{"key":"10","article-title":"Symbolic execution with abstract subsumption checking","author":"anand","year":"0","journal-title":"Proc Of SPIN 2006"},{"key":"7","doi-asserted-by":"crossref","first-page":"373","DOI":"10.1145\/1391469.1391569","article-title":"ifra: instruction footprint recording and analysis for post-silicon bug localization in processors","author":"sung-boem park","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"6","article-title":"The chip is ready. Am i done? On-chip verification using assertion processors","author":"nacif","year":"2003","journal-title":"VLSI-SoC"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159685"},{"key":"4","article-title":"Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug","author":"boule","year":"0","journal-title":"Proc ICC 2006"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78800-3_27"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2009.5351128"}],"event":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","start":{"date-parts":[[2013,10,6]]},"location":"Asheville, NC, USA","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IEEE 31st International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6644329\/6657009\/06657092.pdf?arnumber=6657092","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T01:45:51Z","timestamp":1498095951000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6657092\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iccd.2013.6657092","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}