{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T15:22:33Z","timestamp":1725808953811},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/iccd.2013.6657095","type":"proceedings-article","created":{"date-parts":[[2013,11,11]],"date-time":"2013-11-11T17:22:16Z","timestamp":1384190536000},"page":"511-514","source":"Crossref","is-referenced-by-count":8,"title":["Low-current probabilistic writes for power-efficient STT-RAM caches"],"prefix":"10.1109","author":[{"given":"Nikolaos","family":"Strikos","sequence":"first","affiliation":[]},{"given":"Vasileios","family":"Kontorinis","sequence":"additional","affiliation":[]},{"given":"Xiangyu","family":"Dong","sequence":"additional","affiliation":[]},{"given":"Houman","family":"Homayoun","sequence":"additional","affiliation":[]},{"given":"Dean","family":"Tullsen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"13","article-title":"Simulation and modeling of a simultaneous multithreading processor","author":"tullsen","year":"0","journal-title":"Proceedings of the Computer Measurement Group Conference 1996"},{"key":"14","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"Proc Design Automation Test Europe Conf Exhibition"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973030"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.16"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0091"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2010.2042041"},{"key":"1","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.842903"},{"journal-title":"Process Integration Devices and Structures 2010 Update","year":"0","key":"6"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2185930"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"journal-title":"Designing Giga-scale Memory Systems with STT-RAM","year":"2011","author":"smullen","key":"8"}],"event":{"name":"2013 IEEE 31st International Conference on Computer Design (ICCD)","start":{"date-parts":[[2013,10,6]]},"location":"Asheville, NC, USA","end":{"date-parts":[[2013,10,9]]}},"container-title":["2013 IEEE 31st International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6644329\/6657009\/06657095.pdf?arnumber=6657095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T22:25:44Z","timestamp":1490221544000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6657095\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iccd.2013.6657095","relation":{},"subject":[],"published":{"date-parts":[[2013,10]]}}}