{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T22:46:19Z","timestamp":1747867579568},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/iccd.2014.6974679","type":"proceedings-article","created":{"date-parts":[[2014,12,8]],"date-time":"2014-12-08T17:29:51Z","timestamp":1418059791000},"page":"181-188","source":"Crossref","is-referenced-by-count":4,"title":["Built-in self-test for interposer-based 2.5D ICs"],"prefix":"10.1109","author":[{"given":"Ran","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sudipta","family":"Bhawmik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","first-page":"52","article-title":"Interconnect testing with boundary scan","author":"wagner","year":"1987","journal-title":"IEEE Int Test Conf"},{"key":"13","article-title":"Test and debug strategy for tsmc cowostm stacking process based heterogeneous 3d ic: A silicon case study","author":"goel","year":"2013","journal-title":"IEEE Int Test Conf"},{"key":"14","first-page":"118","article-title":"3D-ic interconnect test, diagnosis, and repair","author":"chi","year":"2013","journal-title":"IEEE VLSI Test Symp"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2013.6604053"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818770"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2011.5898527"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/368434.368603"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/74382.74447"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651906"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/43.170990"},{"journal-title":"IEEE Computer Society IEEE","year":"2001","key":"6"},{"key":"5","article-title":"Challenges and emerging solutions in testing tsvbased 2 1\/2d-And 3d-stacked ics","author":"marinissen","year":"2012","journal-title":"Proc DATE"},{"key":"4","article-title":"Xilinx's 3d (or 2.5d) packaging enables the worlds highest capacity fpga device, and one of the most powerful processors on the market","author":"yannou","year":"2011","journal-title":"3D Packaging"},{"key":"9","first-page":"1","article-title":"Xilinx stacked silicon interconnect technology delivers breakthrough fpga capacity, bandwidth, and power efficiency","author":"dorsey","year":"2010","journal-title":"White paper Virtex-5 FPGAs"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1997.600311"}],"event":{"name":"2014 32nd IEEE International Conference on Computer Design (ICCD)","start":{"date-parts":[[2014,10,19]]},"location":"Seoul, South Korea","end":{"date-parts":[[2014,10,22]]}},"container-title":["2014 IEEE 32nd International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6964907\/6974646\/06974679.pdf?arnumber=6974679","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T01:47:33Z","timestamp":1490320053000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6974679\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iccd.2014.6974679","relation":{},"subject":[],"published":{"date-parts":[[2014,10]]}}}