{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:39:45Z","timestamp":1729654785036,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/iccd.2014.6974732","type":"proceedings-article","created":{"date-parts":[[2014,12,8]],"date-time":"2014-12-08T17:29:51Z","timestamp":1418059791000},"page":"521-524","source":"Crossref","is-referenced-by-count":0,"title":["ScalaHDL: Express and test hardware designs in a Scala DSL"],"prefix":"10.1109","author":[{"given":"Yao","family":"Li","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Antonio Roldao","family":"Lopes","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhouyun","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhengwei","family":"Qi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haibing","family":"Guan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/0167-6423(92)90005-V"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081379"},{"journal-title":"Inkytonik \/ Dsinfo-Bitbucket","year":"2014","key":"10"},{"journal-title":"Silos-Verilog Simulator","year":"2013","key":"1"},{"key":"7","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/92.820756","article-title":"HML, a novel hardware description language and its translation to vhdl","volume":"8","author":"li","year":"2000","journal-title":"IEEE Transactions on very large scale integration Systems"},{"key":"6","doi-asserted-by":"crossref","first-page":"175","DOI":"10.1109\/FPGA.1998.707895","article-title":"Jhdl-An hdl for reconfigurable systems","author":"bellows","year":"1998","journal-title":"IEEE Symp FPGAs for Custom Computing Machines"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/331960.331978"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296459"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"journal-title":"Myhdl","year":"2014","key":"8"}],"event":{"name":"2014 32nd IEEE International Conference on Computer Design (ICCD)","start":{"date-parts":[[2014,10,19]]},"location":"Seoul, South Korea","end":{"date-parts":[[2014,10,22]]}},"container-title":["2014 IEEE 32nd International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6964907\/6974646\/06974732.pdf?arnumber=6974732","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T11:57:54Z","timestamp":1602676674000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6974732"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iccd.2014.6974732","relation":{},"subject":[],"published":{"date-parts":[[2014,10]]}}}