{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:02:09Z","timestamp":1729652529222,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/iccd.2015.7357175","type":"proceedings-article","created":{"date-parts":[[2015,12,17]],"date-time":"2015-12-17T16:57:06Z","timestamp":1450371426000},"page":"635-642","source":"Crossref","is-referenced-by-count":1,"title":["RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory"],"prefix":"10.1109","author":[{"given":"Su Myat Min","family":"Shwe","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kapil","family":"Batra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yusuke","family":"Yachide","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jorgen","family":"Peddersen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5457153"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2013.6509661"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391552"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2007.375276"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-01113-4_4"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2275252"},{"article-title":"Performance simulation of multiprocessor systems","year":"2010","author":"gabor","key":"ref16"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"199","DOI":"10.1007\/978-3-642-11950-7_18","article-title":"A method for accurate high-level performance evaluation of mpsoc architectures using fine-grained generated traces","volume":"5974","author":"plyaskin","year":"2010","journal-title":"Architecture of Computing Systems - ARCS 2010"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2010.5642665"},{"key":"ref19","first-page":"283:1","article-title":"Hardware-based fast exploration of cache hierarchies in application specific mpsocs","author":"nawinne","year":"2014","journal-title":"Proceedings of the Design Automation & Test in Europe Conference DATE"},{"key":"ref4","article-title":"Embedded Systems","author":"bailey","year":"2009","journal-title":"ESL Models and their Application Electronic System Level Design and Verification in Practice"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653959"},{"key":"ref3","article-title":"Systems on Silicon","author":"leibson","year":"2006","journal-title":"Designing SOCs With Configured Cores Unleashing the Tensilica Xtensa and Diamond Cores"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.50"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESTIMedia.2011.6088526"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/RTCSA.2007.21"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.36"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1878961.1878978"},{"article-title":"Dinero iv trace-driven uniprocessor cache simulator","year":"0","author":"edler","key":"ref9"},{"article-title":"High-Performance Embedded Computing: Architectures, Applications, and Methodologies","year":"2007","author":"wolf","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024951"},{"year":"0","key":"ref22","article-title":"SDF3 file format"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2656106.2656111"},{"journal-title":"Tensilica Inc","article-title":"Xtensa Configurable Processors","year":"0","key":"ref24"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488761"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195540"},{"journal-title":"HP","article-title":"Cacti 6.5","year":"0","key":"ref25"}],"event":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","start":{"date-parts":[[2015,10,18]]},"location":"New York City, NY, USA","end":{"date-parts":[[2015,10,21]]}},"container-title":["2015 33rd IEEE International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7347055\/7357071\/07357175.pdf?arnumber=7357175","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T21:56:15Z","timestamp":1498254975000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7357175\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/iccd.2015.7357175","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}