{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,8]],"date-time":"2026-02-08T00:44:57Z","timestamp":1770511497615,"version":"3.49.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,10]]},"DOI":"10.1109\/iccd.2015.7357183","type":"proceedings-article","created":{"date-parts":[[2015,12,17]],"date-time":"2015-12-17T21:57:06Z","timestamp":1450389426000},"page":"696-703","source":"Crossref","is-referenced-by-count":9,"title":["FPGA-SPICE: A simulation-based power estimation framework for FPGAs"],"prefix":"10.1109","author":[{"given":"Xifan","family":"Tang","sequence":"first","affiliation":[]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"14","author":"lewis","year":"2005","journal-title":"The Stratix II Logic and Routing Architecture FPGA"},{"key":"ref11","year":"2008","journal-title":"Stratix IV Device Handbook Version SIV5V1-1 1"},{"key":"ref12","year":"2008","journal-title":"Virtex-5 User Guide UGI90 (v4 0)"},{"key":"ref13","first-page":"135","author":"hutton","year":"2004","journal-title":"Improving FPGA Performance and Area Using an Adaptive Logic Module FPL"},{"key":"ref14","first-page":"52","author":"luu","year":"2014","journal-title":"On Hard Adders and Carry Chains in FPGAs FCCM"},{"key":"ref15","first-page":"155","author":"lemieux","year":"2000","journal-title":"Generating Highly-Routable Sparse Crossbars for PLDs FPGA"},{"key":"ref16","first-page":"59","author":"lemieux","year":"2001","journal-title":"Using Sparse Crossbars Within LUT Clusters FPGA"},{"key":"ref17","year":"0"},{"key":"ref18","year":"0","journal-title":"ABC A System for Squential Synthesis and Verification"},{"key":"ref19","first-page":"86","author":"lee","year":"2006","journal-title":"Interconnect driver design for long wires in field-programmable gate arrays"},{"key":"ref4","first-page":"1712","volume":"24","author":"li","year":"2005","journal-title":"Power Modeling and Characteristics of Field Programmable Gate Arrays IEEE TCAD"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"279","DOI":"10.1145\/1059876.1059881","article-title":"A Detailed Power Modelfor Field-Programmable Gate Arrays","volume":"10","author":"po","year":"2005","journal-title":"ACM TODAES"},{"key":"ref6","author":"betz","year":"1998","journal-title":"Architecture and CAD for Deep-Submicron FPGAs"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412139"},{"key":"ref8","first-page":"227","author":"luu","year":"2011","journal-title":"Architecture Description and Packing for Logic Blocks with Hierarchy Modes and Complex Interconnect FPGA"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2145694.2145708"},{"key":"ref2","first-page":"87","author":"lamoureux","year":"2006","journal-title":"Activity Estimation for Field-Programmable Gate Arrays IEEE FPL"},{"key":"ref1","first-page":"446","volume":"2","author":"njam","year":"1994","journal-title":"A Survey of Power Estimation Techniques in VLSI Circuits IEEE TVLSI"},{"key":"ref9","author":"vladimirescu","year":"2012","journal-title":"The SPICE Book"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645511"},{"key":"ref22","year":"2011","journal-title":"ITRS-interconnect"},{"key":"ref21","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"ref24","year":"0","journal-title":"Predictive Technology Model"},{"key":"ref23","author":"yang","year":"1991","journal-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3 0"}],"event":{"name":"2015 33rd IEEE International Conference on Computer Design (ICCD)","location":"New York City, NY, USA","start":{"date-parts":[[2015,10,18]]},"end":{"date-parts":[[2015,10,21]]}},"container-title":["2015 33rd IEEE International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7347055\/7357071\/07357183.pdf?arnumber=7357183","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T01:56:17Z","timestamp":1498269377000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7357183\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,10]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/iccd.2015.7357183","relation":{},"subject":[],"published":{"date-parts":[[2015,10]]}}}