{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T20:36:09Z","timestamp":1730234169787,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/iccd.2016.7753338","type":"proceedings-article","created":{"date-parts":[[2016,11,24]],"date-time":"2016-11-24T16:40:00Z","timestamp":1480005600000},"page":"536-543","source":"Crossref","is-referenced-by-count":4,"title":["BADGR: A practical GHR implementation for TAGE branch predictors"],"prefix":"10.1109","author":[{"given":"David J.","family":"Schlais","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mikko H.","family":"Lipasti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Championship branch prediction (cbp-4)","article-title":"T. J. of Instruction-Level Parallelism","year":"2014","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2024716.2024718"},{"key":"ref12","article-title":"Cacti 5.0","author":"thoziyoor","year":"2007","journal-title":"Tech Rep HPL-2007-167"},{"journal-title":"2nd jilp workshop on computer architecture competitions (jwac-2) Championship branch prediction","article-title":"T. J. of Instruction-Level Parallelism","year":"2015","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.32"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/BF02699883"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1998.742787"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1455650.1455654"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1996.566457"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1998.694768"},{"key":"ref4","article-title":"A 64 kbytes isl-tage branch predictor","author":"seznec","year":"2011","journal-title":"JWAC-2 Championship Branch Prediction"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749750"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310786"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003559"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995713"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253186"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2011.6081385"},{"key":"ref1","article-title":"A 256 kbits 1-tage branch predictor","volume":"9","author":"seznec","year":"2007","journal-title":"Journal of Instruction-Level Parallelism (JILP) Special Issue The Second Championship Branch Prediction Competition (CBP-2)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155635"}],"event":{"name":"2016 IEEE 34th International Conference on Computer Design (ICCD)","start":{"date-parts":[[2016,10,2]]},"location":"Scottsdale, AZ, USA","end":{"date-parts":[[2016,10,5]]}},"container-title":["2016 IEEE 34th International Conference on Computer Design (ICCD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7742853\/7753252\/07753338.pdf?arnumber=7753338","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,12,21]],"date-time":"2016-12-21T17:19:30Z","timestamp":1482340770000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7753338\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/iccd.2016.7753338","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}