{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T19:01:11Z","timestamp":1725735671104},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,1,6]],"date-time":"2024-01-06T00:00:00Z","timestamp":1704499200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,6]],"date-time":"2024-01-06T00:00:00Z","timestamp":1704499200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,1,6]]},"DOI":"10.1109\/icce59016.2024.10444234","type":"proceedings-article","created":{"date-parts":[[2024,2,28]],"date-time":"2024-02-28T13:47:20Z","timestamp":1709128040000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Hardware Accelerated Matrix Multiplication for Embedded Systems"],"prefix":"10.1109","author":[{"given":"Patrick","family":"Arndt","sequence":"first","affiliation":[{"name":"University of Applied Sciences,Fachhochschule S&#x00FC;dwestfalen,Hagen,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karol","family":"Niewiadomski","sequence":"additional","affiliation":[{"name":"University of Applied Sciences,Fachhochschule S&#x00FC;dwestfalen,Hagen,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dietmar","family":"Tutsch","sequence":"additional","affiliation":[{"name":"University of Wuppertal,Chair of Automation \/ Computer Science,Wuppertal,Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","first-page":"71","article-title":"Towards a dynamically reconfigurable automotive control system architecture","volume-title":"Embedded System Design: Topics, Techniques and Trends","author":"R. A"},{"volume-title":"TensorFloat-32 in the A100 GPU Accelerates AI Training, HPC up to 20x","year":"2020","key":"ref2"},{"volume-title":"NVIDIA Ampere-Architektur","year":"2023","key":"ref3"},{"volume-title":"NVIDIA H100 Tensor Core GPU Architecture","year":"2023","key":"ref4"},{"volume-title":"Nvidia\u2019s H100: Funny L2, and Tons of Bandwidth","year":"2023","key":"ref6"},{"volume-title":"The Design Warrior\u2019s Guide to FPGAs: Devices, Tools and Flows","year":"2004","author":"Maxfield","key":"ref7"},{"volume-title":"NIOS\u00ae II Processor Reference Guide","year":"2023","key":"ref8"},{"volume-title":"Avalon\u00ae Interface Specifications","year":"2019","key":"ref9"},{"volume-title":"Nios II Custom Instruction User Guide","year":"2020","key":"ref10"},{"volume-title":"Multiplizierer (Digitaltechnik)","year":"2023","key":"ref11"}],"event":{"name":"2024 IEEE International Conference on Consumer Electronics (ICCE)","start":{"date-parts":[[2024,1,6]]},"location":"Las Vegas, NV, USA","end":{"date-parts":[[2024,1,8]]}},"container-title":["2024 IEEE International Conference on Consumer Electronics (ICCE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10444098\/10444131\/10444234.pdf?arnumber=10444234","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,13]],"date-time":"2024-03-13T17:41:00Z","timestamp":1710351660000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10444234\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1,6]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/icce59016.2024.10444234","relation":{},"subject":[],"published":{"date-parts":[[2024,1,6]]}}}