{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,7]],"date-time":"2026-08-07T23:53:19Z","timestamp":1786146799225,"version":"3.56.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/iccicct.2015.7475300","type":"proceedings-article","created":{"date-parts":[[2017,3,2]],"date-time":"2017-03-02T21:55:11Z","timestamp":1488491711000},"page":"335-339","source":"Crossref","is-referenced-by-count":6,"title":["Design and implementation of 1 GHz Current Starved Voltage Controlled Oscillator (VCO) for PLL using 90nm CMOS technology"],"prefix":"10.1109","author":[{"given":"Vishwanath","family":"Muddi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kunjan D.","family":"Shinde","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Shivaprasad B K","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","first-page":"355","article-title":"CMOS Circuit Design, Layout and Simulation","author":"jacob","year":"0","journal-title":"IEEE Press Series on Microelectronics Systems"},{"key":"ref3","author":"hodges","year":"1988","journal-title":"Analysis and Design of Digital Integrated Circuits"},{"key":"ref10","first-page":"212","article-title":"Analysis and Design of the IGHz PLL for Fast Phase and Frequency Acquisition","author":"panda","year":"2011","journal-title":"Proc of International Conference on Electronic System India"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/ecej:19920037"},{"key":"ref5","article-title":"Ultra Low Voltage Controlled Oscillator","author":"deen","year":"0","journal-title":"Electrical and Computer Engineering Department CRL 226 McMaster University"},{"key":"ref8","doi-asserted-by":"crossref","DOI":"10.1109\/ITNG.2006.50","article-title":"Design of a 1GHz Digital PLL Using 0.18um CMOS Technology","author":"janardhan","year":"2006","journal-title":"Proc of the Third Int Conf on Information Technology"},{"key":"ref7","article-title":"Analysis & Design the of Analog Integrated Circuits","author":"gray","year":"1993"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.90035"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.5121\/vlsic.2012.3513"},{"key":"ref1","first-page":"283","author":"razavi","year":"0","journal-title":"Monolithic Phase Locked Loops and Clock Recovery circuits Theory and Design"}],"event":{"name":"2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","location":"Kumaracoil, India","start":{"date-parts":[[2015,12,18]]},"end":{"date-parts":[[2015,12,19]]}},"container-title":["2015 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7469254\/7475237\/07475300.pdf?arnumber=7475300","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T14:42:35Z","timestamp":1602686555000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/7475300"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iccicct.2015.7475300","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}