{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:13:00Z","timestamp":1781885580292,"version":"3.54.5"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/iccnc.2014.6785453","type":"proceedings-article","created":{"date-parts":[[2014,4,17]],"date-time":"2014-04-17T18:04:24Z","timestamp":1397757864000},"page":"878-884","source":"Crossref","is-referenced-by-count":6,"title":["High-throughput programmable systolic array FFT architecture and FPGA implementations"],"prefix":"10.1109","author":[{"given":"J.","family":"Greg Nash","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"15","year":"2007","journal-title":"Altera DFT\/IDFT Reference Design"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/WCNC.2012.6214486"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/11.992857"},{"key":"14","doi-asserted-by":"crossref","first-page":"647","DOI":"10.1109\/TCSII.2010.2050950","article-title":"Low-computation-cycle, power-efficient, and reconfigurable design of recursive DFT for portable digital radio mondiale receiver","volume":"57","author":"lai","year":"2010","journal-title":"IEEE Trans Circuits and Systems II"},{"key":"11","first-page":"1546","article-title":"Hardware implementation of the DFT with non-power-of-two problem size","author":"milder","year":"0","journal-title":"Proc 2010 IEEE Int Conf Acoustics Speech Sig Proc"},{"key":"12","year":"2011","journal-title":"Xilinx Discrete Fourier Transform v3 1"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2037262"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1155\/2011\/136319"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISWPC.2010.5483715"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5117960"},{"key":"7","doi-asserted-by":"crossref","first-page":"4640","DOI":"10.1109\/TSP.2005.859216","article-title":"Computationally efficient systolic architecture for computing the discrete Fourier transform","volume":"53","author":"greg nash","year":"2005","journal-title":"IEEE Trans Sig Process"},{"key":"6","author":"kung","year":"1988","journal-title":"VLSI Array Processors"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/529512"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-008-0328-x"},{"key":"9","author":"kung","year":"1988","journal-title":"VLSI Array Processors"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2007.366162"}],"event":{"name":"2014 International Conference on Computing, Networking and Communications (ICNC)","location":"Honolulu, HI, USA","start":{"date-parts":[[2014,2,3]]},"end":{"date-parts":[[2014,2,6]]}},"container-title":["2014 International Conference on Computing, Networking and Communications (ICNC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6778476\/6785290\/06785453.pdf?arnumber=6785453","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T11:46:02Z","timestamp":1498131962000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6785453\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iccnc.2014.6785453","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}