{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:57:24Z","timestamp":1729619844003,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/iccsce.2015.7482148","type":"proceedings-article","created":{"date-parts":[[2016,6,2]],"date-time":"2016-06-02T13:07:28Z","timestamp":1464872848000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["FPGA implementation of 64 bit Secure Force algorithm using full loop-unroll architecture"],"prefix":"10.1109","author":[{"given":"Shujaat","family":"Khan","sequence":"first","affiliation":[]},{"given":"M. Sohail","family":"Ibrahim","sequence":"additional","affiliation":[]},{"given":"Haseeb","family":"Amjad","sequence":"additional","affiliation":[]},{"given":"Kafeel Ahmed","family":"Khan","sequence":"additional","affiliation":[]},{"given":"Mansoor","family":"Ebrahim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Fair and comprehensive methodology for comparing hardware performance of fourteen round two SHA-3 candidates using FPGAs","author":"kris","year":"2010","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TENCON.2007.4429126"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2008.4746393"},{"key":"ref13","first-page":"427","article-title":"AES on FPGA from the fastest to the smallest","author":"tim","year":"2005","journal-title":"Cryptographic Hardware and Embedded Systems-CHES 2005"},{"key":"ref14","article-title":"Implementation of the AES-128 on Virtex-5 FPGAs","author":"philippe","year":"2008","journal-title":"Progress in Cryptology AFRICACRYPT"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1016\/j.jnca.2014.09.006","article-title":"A comprehensive survey of modern symmetric cryptographic solutions for resource constrained environments","volume":"49","author":"jia hao","year":"2015","journal-title":"Journal of Network and Computer Applications"},{"journal-title":"Altera &#x00AE; Cyclone II Architecture","year":"0","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICECTECH.2011.5941780"},{"article-title":"FPGA Comparative Analysis","year":"0","author":"ognjen","key":"ref18"},{"journal-title":"Dynamic Power Reduction in Flash FPGAs AC323 Microsemi","year":"0","key":"ref19"},{"key":"ref4","first-page":"319","article-title":"Very compact FPGA implementation of the AES algorithm","author":"pawel","year":"2003","journal-title":"Cryptographic Hardware and Embedded Systems - CHES 2003"},{"key":"ref3","first-page":"87","article-title":"New Version of AES-ECC Encryption System Based on FPGA in WSNs","volume":"9 1","author":"bing","year":"2015","journal-title":"Journal of Software Engineering"},{"key":"ref6","article-title":"Secure Force: A low-complexity cryptographic algorithm for Wireless Sensor Network (WSN)","author":"mansoor","year":"2013","journal-title":"Control System Computing and Engineering (ICCSCE) 2013 IEEE International Conference on"},{"key":"ref5","first-page":"575","article-title":"Exploring area\/delay tradeoffs in an AES FPGA implementation","author":"joseph","year":"2004","journal-title":"Field Programmable Logic and Application"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/948117.948120"},{"article-title":"Performance Evaluation of Secure Force Symmetric Key Algorithm","year":"2015","author":"shujaat","key":"ref7"},{"key":"ref2","first-page":"334","article-title":"Efficient implementation of Rijndael encryption in reconfigurable hardware: improvements and design tradeoffs","author":"francois-xavier","year":"2003","journal-title":"Cryptographic Hardware and Embedded Systems - CHES 2003"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/92.931230"},{"key":"ref9","article-title":"Partial reconfigurable FIR filtering system using distributed arithmetic","author":"daniel","year":"2010","journal-title":"International Journal of Reconfigurable Computing"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1151414.1151417"},{"article-title":"Energy Efficiency Analysis and Implementation of AES on an FPGA","year":"2009","author":"david","key":"ref22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2006.40"}],"event":{"name":"2015 IEEE International Conference on Control System, Computing and Engineering (ICCSCE)","start":{"date-parts":[[2015,11,27]]},"location":"Penang, Malaysia","end":{"date-parts":[[2015,11,29]]}},"container-title":["2015 IEEE International Conference on Control System, Computing and Engineering (ICCSCE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7468595\/7482142\/07482148.pdf?arnumber=7482148","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,24]],"date-time":"2017-06-24T11:36:25Z","timestamp":1498304185000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7482148\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/iccsce.2015.7482148","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}