{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T20:59:44Z","timestamp":1776977984025,"version":"3.51.4"},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T00:00:00Z","timestamp":1751500800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T00:00:00Z","timestamp":1751500800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,7,3]]},"DOI":"10.1109\/icecet63943.2025.11472239","type":"proceedings-article","created":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T19:42:35Z","timestamp":1775763755000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["The floorplan utilization definition using neural networks"],"prefix":"10.1109","author":[{"given":"Kang","family":"Li","sequence":"first","affiliation":[{"name":"Xidian University,Faculty of Integrated Circuit,Xi&#x2019;an,China"}]},{"given":"Xuefeng","family":"Zheng","sequence":"additional","affiliation":[{"name":"Xidian University,Faculty of Integrated Circuit,Xi&#x2019;an,China"}]},{"given":"Nazeli","family":"Melikyan","sequence":"additional","affiliation":[{"name":"National Polytechnic University of Armenia,Synopsys Armenia CJSC,Yerevan,Armenia"}]},{"given":"Artur","family":"Ghazaryan","sequence":"additional","affiliation":[{"name":"Synopsys Armenia CJSC,Yerevan,Armenia"}]},{"given":"Tigran","family":"Grigoryan","sequence":"additional","affiliation":[{"name":"Synopsys Armenia CJSC,Yerevan,Armenia"}]}],"member":"263","reference":[{"key":"ref1","first-page":"996","article-title":"An Overview of CMOS Technology Scaling Trends and Challenges","volume":"40","author":"Saremi","year":"2019","journal-title":"IEEE Electron Device Letters"},{"issue":"6","key":"ref2","first-page":"841","article-title":"A Robust SPIDER-Based Approach Against Back-End Process Variation for 7-nm FinFET Standard Cell Layout. IET Circuits, Devices & Systems","volume":"14","author":"Lee","year":"2020"},{"key":"ref3","volume-title":"System Design: A Practical Guide with SpecC","author":"Gajski","year":"2005"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0965-7"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980084"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.3390\/electronics10161930"},{"key":"ref7","article-title":"ICCAD-2017 CAD Contest in FPGA Placement Routing and Benchmark Suite","author":"Liu","year":"2018","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1126\/science.220.4598.671"},{"key":"ref9","first-page":"367","article-title":"A Genetic Approach to the Placement of Macro-Cells in VLSI-Circuits","volume-title":"Proceedings of 3rd International Workshop on Biologically Inspired Approaches to Advanced Information Technology (Bio-ADIT 2004)","author":"Eschermann"},{"key":"ref10","volume-title":"Evolutionary Algorithms for Solving Multi-Objective Problems","author":"Coello","year":"2007"},{"issue":"6","key":"ref11","article-title":"Simulated annealing based placement algorithms and research challenges: A survey","volume":"3","author":"Pttanaik","year":"2012","journal-title":"Journal of Global research and computer science"}],"event":{"name":"2025 5th International Conference on Electrical, Computer and Energy Technologies (ICECET)","location":"Paris, France","start":{"date-parts":[[2025,7,3]]},"end":{"date-parts":[[2025,7,6]]}},"container-title":["2025 5th International Conference on Electrical, Computer and Energy Technologies (ICECET)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11471878\/11471697\/11472239.pdf?arnumber=11472239","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T19:58:51Z","timestamp":1776974331000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11472239\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,7,3]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/icecet63943.2025.11472239","relation":{},"subject":[],"published":{"date-parts":[[2025,7,3]]}}}