{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T01:23:57Z","timestamp":1729646637033,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icecs.2002.1046197","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T19:45:08Z","timestamp":1056570308000},"page":"461-465","source":"Crossref","is-referenced-by-count":0,"title":["An efficient test relaxation technique for combinational circuits based on critical path tracing"],"prefix":"10.1109","volume":"2","author":[{"given":"A.","family":"El-Maleh","sequence":"first","affiliation":[]},{"given":"A.","family":"Al-Suwaiyan","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1998.670850"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.3140"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/6.542274"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.662677"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639597"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743146"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743186"},{"key":"ref3","first-page":"54","article-title":"A Geometric-Primitive-Based Compression Scheme for Testing Systems-on-a-Chip","author":"ei-maleh","year":"2001","journal-title":"Proc IEEE VLSI Test Symposium"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1998.144279"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/43.536711","article-title":"HOPE: An Effecient Parallel Fault Simulator for Synchronous Sequential Circuits","volume":"15","author":"lee","year":"1996","journal-title":"IEEE Trans on Computer Aided Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.469663"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519510"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923416"},{"article-title":"Digital System Testing and Testable Design.","year":"1990","author":"abramovici","key":"ref9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843834"}],"event":{"name":"9th International Conference on Electronics, Circuits and Systems (ICECS 2002)","acronym":"ICECS-02","location":"Dubrovnik, Croatia"},"container-title":["9th International Conference on Electronics, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8101\/22423\/01046197.pdf?arnumber=1046197","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:43:47Z","timestamp":1497552227000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1046197\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/icecs.2002.1046197","relation":{},"subject":[]}}