{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:48:57Z","timestamp":1761580137636,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icecs.2002.1046254","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T23:45:08Z","timestamp":1056584708000},"page":"657-660","source":"Crossref","is-referenced-by-count":11,"title":["A low-power threshold logic family"],"prefix":"10.1109","volume":"2","author":[{"given":"M.","family":"Padure","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Cotofana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Vassiliadis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Dan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Bodea","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"!Compact Transistor Modelling for Circuit Designi","author":"de graaff","year":"1990","journal-title":"Springer-Verlag"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1080\/002072198134724"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/16.137325"},{"key":"ref6","article-title":"ìThreshold Logic and its Applicationsi","author":"muroga","year":"1971","journal-title":"J Wiley and Sons Inc"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.508212"},{"key":"ref5","first-page":"63","article-title":"ìBit-sliced median Ýlterde-sign based on majority gateî","volume":"139","author":"lee","year":"0","journal-title":"IEE Proceedings-G"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.102688"},{"key":"ref7","first-page":"1141","article-title":"ìA compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gatest","volume":"31","author":"leblebici","year":"0","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref2","first-page":"1118","volume":"9","author":"cotofana","year":"0","journal-title":"ìPeriodic Symmetric Functions Serial Addition and Multiplication with Neural Networksî"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1669","DOI":"10.1109\/5.58350","article-title":"ìNeural Computing of Arithmetic Functionsî","volume":"17","author":"siu","year":"1990","journal-title":"Proc IEEE"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/el:19951471"}],"event":{"name":"9th International Conference on Electronics, Circuits and Systems (ICECS 2002)","acronym":"ICECS-02","location":"Dubrovnik, Croatia"},"container-title":["9th International Conference on Electronics, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8101\/22423\/01046254.pdf?arnumber=1046254","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:43:46Z","timestamp":1497566626000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1046254\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/icecs.2002.1046254","relation":{},"subject":[]}}