{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T01:46:32Z","timestamp":1755999992496,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icecs.2002.1046256","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T19:45:08Z","timestamp":1056570308000},"page":"665-668","source":"Crossref","is-referenced-by-count":17,"title":["A full adder implementation using SET based linear threshold gates"],"prefix":"10.1109","volume":"2","author":[{"given":"C.","family":"Lageweg","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Cotofana","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Vassiliadis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1063\/1.360107"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1080\/002072199133256"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/43.658562"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/IWV.2001.923145"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1063\/1.352206"},{"key":"ref8","first-page":"1383","article-title":"iAchieving Fanout Capabilities in Single Electron Encoded Logic Networks,î","author":"lageweg","year":"2001","journal-title":"6th International Conference on Solid-state and IC Technology (ICSICT)"},{"year":"1998","author":"wasshuber","journal-title":"About single-electron devices and circuits","key":"ref7"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/5.752518"},{"key":"ref9","first-page":"227","article-title":"ìLow Weight and Fan-In Neural Networks for Basic Arithmetic Operations,î","author":"cotofana","year":"1997","journal-title":"Congress on Scientific Computation Modelling and Applied Mathematics Volume 4 Artificial Intelligence and Computer Science"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"486","DOI":"10.1109\/5.573737","article-title":"ìCMOS Scaling into the Nanometer Regimeî","volume":"85","author":"taur","year":"1997","journal-title":"Proceeding of the IEEE"}],"event":{"acronym":"ICECS-02","name":"9th International Conference on Electronics, Circuits and Systems (ICECS 2002)","location":"Dubrovnik, Croatia"},"container-title":["9th International Conference on Electronics, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8101\/22423\/01046256.pdf?arnumber=1046256","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:43:50Z","timestamp":1497552230000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1046256\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/icecs.2002.1046256","relation":{},"subject":[]}}