{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:46:34Z","timestamp":1729644394761,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icecs.2004.1399703","type":"proceedings-article","created":{"date-parts":[[2005,3,31]],"date-time":"2005-03-31T18:26:51Z","timestamp":1112293611000},"page":"403-406","source":"Crossref","is-referenced-by-count":3,"title":["Design and modelling of network on chip interconnects using transmission lines"],"prefix":"10.1109","author":[{"given":"A.","family":"Barger","sequence":"first","affiliation":[]},{"given":"D.","family":"Goren","sequence":"additional","affiliation":[]},{"given":"A.","family":"Kolodny","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/T-ED.1983.21093"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/DAC.2003.1219114"},{"key":"12","article-title":"Modelling methodology for on-chip coplanar transmission lines over the lossy silicon substrate","author":"goren","year":"2003","journal-title":"Proc IEEE Signal Propagation Interconnect Conf"},{"key":"3","article-title":"Interconnect intellectual property for network-on-chip (NOC)","author":"liu","year":"2003","journal-title":"Journal of System Architecture"},{"key":"2","first-page":"892","volume":"4","author":"liu","year":"2003","journal-title":"A Global Wire Planning Scheme for Network-on-chip"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1145\/378239.379048"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/SPI.2002.258319"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1007\/b105353"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1007\/978-1-4615-1685-9_13"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/ASIC.2002.1158092"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/DATE.2000.840047"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/DATE.2002.998391"},{"key":"8","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.sysarc.2003.07.004","article-title":"QoS architecture and design process for cost effective network on chip","volume":"50","author":"bolotin","year":"2004","journal-title":"Journal of Systems Architecture Special Issue on Network on Chip"}],"event":{"name":"2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.","location":"Tel Aviv, Israel"},"container-title":["Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9627\/30421\/01399703.pdf?arnumber=1399703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T17:51:06Z","timestamp":1497635466000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1399703\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/icecs.2004.1399703","relation":{},"subject":[]}}