{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T00:05:20Z","timestamp":1773792320798,"version":"3.50.1"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,12]]},"DOI":"10.1109\/icecs.2007.4510993","type":"proceedings-article","created":{"date-parts":[[2008,5,5]],"date-time":"2008-05-05T16:21:05Z","timestamp":1210004465000},"page":"314-317","source":"Crossref","is-referenced-by-count":1,"title":["HLS design flow for the synthesis of multimode systems under multiple constraints"],"prefix":"10.1109","author":[{"given":"Bertrand","family":"Le Gal","sequence":"first","affiliation":[{"name":"IMS Laboratory, CNRS UMR 5218, ENSEIRB, Bordeaux 1 University, France. Email: bertrand.legal@ims-bordeaux.fr"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lilian","family":"Bossuet","sequence":"additional","affiliation":[{"name":"IMS Laboratory, CNRS UMR 5218, ENSEIRB, Bordeaux 1 University, France. Email: lilian.bossuet@ims-bordeaux.fr"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shafqat","family":"Khan","sequence":"additional","affiliation":[{"name":"IRISA Laboratory, R2D2, ENSSAT, Lannion, France. Email: shafqat.khan@irisa.fr"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emmanuel","family":"Casseau","sequence":"additional","affiliation":[{"name":"IRISA Laboratory, R2D2, ENSSAT, Lannion, France. Email: emmanuel.casseau@irisa.fr"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1053271.1053278"},{"key":"ref3","author":"elliott","year":"2000","journal-title":"Understanding Behavioral Synthesis A Practical Guide to High-Level Design"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339528"},{"key":"ref5","article-title":"Highly flexible multimode digital signal processing systems using adaptable components and controllers","volume":"2006","author":"kumar","year":"2006","journal-title":"EURASIP Journal on Applied Signal Processing"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2002.1115384"},{"key":"ref2","author":"gajski","year":"1992","journal-title":"High-Level Synthesis Introduction to Chip and System Design"},{"key":"ref1","article-title":"C-based rapid prototyping for digital signal processing","author":"casseau","year":"2005","journal-title":"Proceedings of EUSIPCO"}],"event":{"name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","location":"Marrakech, Morocco","start":{"date-parts":[[2007,12,11]]},"end":{"date-parts":[[2007,12,14]]}},"container-title":["2007 14th IEEE International Conference on Electronics, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4456901\/4510892\/04510993.pdf?arnumber=4510993","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:21:03Z","timestamp":1773778863000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4510993\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/icecs.2007.4510993","relation":{},"subject":[],"published":{"date-parts":[[2007,12]]}}}