{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T00:01:54Z","timestamp":1773792114204,"version":"3.50.1"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2007,12,1]],"date-time":"2007-12-01T00:00:00Z","timestamp":1196467200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,12]]},"DOI":"10.1109\/icecs.2007.4511258","type":"proceedings-article","created":{"date-parts":[[2008,5,5]],"date-time":"2008-05-05T16:21:05Z","timestamp":1210004465000},"page":"1388-1391","source":"Crossref","is-referenced-by-count":0,"title":["A Low-Noise Fractional-N Frequency Synthesiser Using A Very Fast Noise Shaper"],"prefix":"10.1109","author":[{"given":"Hongyu","family":"Wang","sequence":"first","affiliation":[{"name":"Department of Electronic and Electrical Engineering, University College London, London, United Kingdom. h.wang@ee.ucl.ac.uk"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul V.","family":"Brennan","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering, University College London, London, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dai","family":"Jiang","sequence":"additional","affiliation":[{"name":"Department of Electronic and Electrical Engineering, University College London, London, United Kingdom"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.229400"},{"key":"ref3","article-title":"Frequency synthesizer","author":"wells","year":"1986","journal-title":"U S Patent"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.871322"},{"key":"ref6","article-title":"PLL performance, simulation and design","author":"banerjee","year":"1998","journal-title":"National Semiconductor"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.1015680"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20040189"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el:20000059"},{"key":"ref2","author":"gibbs","year":"1978","journal-title":"Frequency Domain Yields its Data to Phase-Locked Synthesizer Electronics"},{"key":"ref9","article-title":"Phase-Locked Loops: Principles and Practice","author":"brennan","year":"1996"},{"key":"ref1","article-title":"Frequency synthesis by Phase Lock","author":"egan","year":"1981"}],"event":{"name":"2007 14th IEEE International Conference on Electronics, Circuits and Systems","location":"Marrakech, Morocco","start":{"date-parts":[[2007,12,11]]},"end":{"date-parts":[[2007,12,14]]}},"container-title":["2007 14th IEEE International Conference on Electronics, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4456901\/4510892\/04511258.pdf?arnumber=4511258","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:20:03Z","timestamp":1773778803000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4511258\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,12]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/icecs.2007.4511258","relation":{},"subject":[],"published":{"date-parts":[[2007,12]]}}}