{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T13:58:20Z","timestamp":1725458300133},"reference-count":18,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,8]]},"DOI":"10.1109\/icecs.2008.4674972","type":"proceedings-article","created":{"date-parts":[[2008,11,25]],"date-time":"2008-11-25T10:45:25Z","timestamp":1227609925000},"page":"790-793","source":"Crossref","is-referenced-by-count":0,"title":["A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias"],"prefix":"10.1109","author":[{"given":"Chih-Hsing","family":"Lin","sequence":"first","affiliation":[]},{"given":"Ching-Te","family":"Chiu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","first-page":"371","article-title":"a cmos 2.4 ghz delay-locked loop based programmable frequency multiplier","author":"weng","year":"2006","journal-title":"IEEE ICCE"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377888"},{"key":"15","first-page":"72","article-title":"a 2.2 ghz programmable dll-based frequency multiplier for soc applications","author":"cheng","year":"2004","journal-title":"IEEE AP-ASIC2004"},{"key":"16","first-page":"177","article-title":"low jitter butterworth delay-locked loops","author":"chang","year":"2003","journal-title":"IEEE VLSI Circuit"},{"key":"13","first-page":"257","article-title":"a 10 gb\/s wide-band current-mode logic i\/o interface for high-speed interconnect in 0.18m cmos technology","author":"kao","year":"2005","journal-title":"IEEE ISSOC"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/4.760373"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955030"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.800922"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.826820"},{"year":"0","key":"2"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MCOM.2003.1252802"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2005.1554458"},{"key":"7","first-page":"1871","article-title":"breaking the power-delay tradeoff design of low-power high-speed mos current-mode","author":"badel","year":"2007","journal-title":"IEEE ISCAS"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/4.890315"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2005.1635296"},{"key":"4","first-page":"330","article-title":"a 1-4 ghz dll based low-jitter multi-phase clock generator for low-band ultra-wideband application","author":"liu","year":"2004","journal-title":"IEEE Asia-Pacific Conf on Adv Sys Integrated Circuits"},{"key":"9","first-page":"141","article-title":"design of ultra low power current mode logics with adaptive body bias","author":"hsu","year":"2007","journal-title":"IEEE ISSOC"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377878"}],"event":{"name":"2008 15th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2008)","start":{"date-parts":[[2008,8,31]]},"location":"St. Julien's, Malta","end":{"date-parts":[[2008,9,3]]}},"container-title":["2008 15th IEEE International Conference on Electronics, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4664823\/4674773\/04674972.pdf?arnumber=4674972","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T12:02:04Z","timestamp":1602676924000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4674972"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,8]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/icecs.2008.4674972","relation":{},"subject":[],"published":{"date-parts":[[2008,8]]}}}