{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:51:52Z","timestamp":1729673512451,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,12]]},"DOI":"10.1109\/icecs.2009.5410896","type":"proceedings-article","created":{"date-parts":[[2010,2,17]],"date-time":"2010-02-17T15:26:26Z","timestamp":1266420386000},"page":"439-442","source":"Crossref","is-referenced-by-count":2,"title":["A multi level functional verification of multistage interconnection network for MPSOC"],"prefix":"10.1109","author":[{"given":"Yassine","family":"Aydi","sequence":"first","affiliation":[]},{"given":"Ramzi","family":"Tligue","sequence":"additional","affiliation":[]},{"given":"Maissa","family":"Elleuch","sequence":"additional","affiliation":[]},{"given":"Mohamed","family":"Abid","sequence":"additional","affiliation":[]},{"given":"Jean-Luc","family":"Dekeyser","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"ref3","first-page":"565","article-title":"Floorplan-aware automated synthesis of bus-based communication architectures","author":"pasricha","year":"2005","journal-title":"Proc of 42nd Design Automation Conference"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1016\/0304-3975(86)90084-8","article-title":"A unified theory of interconnection network","volume":"48","author":"kruskal","year":"1986","journal-title":"Theoretical Computer Science"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676802"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1217975.1217985"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1147\/sj.342.0185"},{"key":"ref12","first-page":"23","article-title":"ACL2: An industrial strength version of nqthm","volume":"23","author":"kaufmann","year":"1996","journal-title":"IEEE Transactions on Software Engineering"},{"key":"ref8","article-title":"Dynamicity Analysis of Delta MINs for MPSOC Architectures","author":"aydi","year":"2007","journal-title":"STA’07"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2007.4497674"},{"key":"ref2","first-page":"681","article-title":"The future of multiprocessor systems-on-chips","author":"wolf","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FDL.2008.4641461"},{"article-title":"Multiprocessor Systems-on-Chips","year":"2004","author":"jerraya","key":"ref1"}],"event":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2009)","start":{"date-parts":[[2009,12,13]]},"location":"Yasmine Hammamet","end":{"date-parts":[[2009,12,16]]}},"container-title":["2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5403223\/5410749\/05410896.pdf?arnumber=5410896","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T00:57:37Z","timestamp":1497833857000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5410896\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icecs.2009.5410896","relation":{},"subject":[],"published":{"date-parts":[[2009,12]]}}}