{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T22:14:38Z","timestamp":1730240078276,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,12]]},"DOI":"10.1109\/icecs.2009.5411009","type":"proceedings-article","created":{"date-parts":[[2010,2,17]],"date-time":"2010-02-17T20:26:26Z","timestamp":1266438386000},"page":"339-342","source":"Crossref","is-referenced-by-count":9,"title":["Asynchronous design: A promising paradigm for electronic circuits and systems"],"prefix":"10.1109","author":[{"given":"Eslam","family":"Yahya","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laurent","family":"Fesquet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals","volume":"11","author":"fraidy bouesse","year":"2005","journal-title":"VLSI-SoC"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.164"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.16"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2009.12"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/piee.1976.0212"},{"key":"ref15","article-title":"Synchronization and Arbitration in Digital Systems","author":"david","year":"0","journal-title":"Publisher (WileyBlackwell 2007)"},{"key":"ref16","first-page":"119","article-title":"M: a low-power FPGA based on autonomous fine-grain power-gating","author":"hariyama","year":"2009","journal-title":"ASP-DAC"},{"key":"ref17","first-page":"390","article-title":"Dynamic Voltage Scheduling for Real Time Asynchronous Systems","author":"mohammed","year":"2002","journal-title":"PATMOS"},{"year":"0","key":"ref18"},{"year":"0","key":"ref19","article-title":"Handshake solutions"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727058"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1998.666497"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CONECT.2003.1231470"},{"key":"ref5","first-page":"465","article-title":"Standard-Logic Quasi Delay Insensitive Registers","author":"yahya","year":"0","journal-title":"VLSI-SOC'08"},{"year":"0","key":"ref8","article-title":"Fulcrum Microsystems"},{"year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.884049"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"year":"2006","key":"ref9"},{"year":"0","key":"ref20","article-title":"Silistix"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2008.4675095"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1991.206431"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/54.350687"}],"event":{"name":"2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)","start":{"date-parts":[[2009,12,13]]},"location":"Yasmine Hammamet, Tunisia","end":{"date-parts":[[2009,12,16]]}},"container-title":["2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5403223\/5410749\/05411009.pdf?arnumber=5411009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T03:33:03Z","timestamp":1489894383000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5411009\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,12]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/icecs.2009.5411009","relation":{},"subject":[],"published":{"date-parts":[[2009,12]]}}}