{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T03:37:13Z","timestamp":1729654633784,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/icecs.2011.6122212","type":"proceedings-article","created":{"date-parts":[[2012,1,11]],"date-time":"2012-01-11T17:00:31Z","timestamp":1326301231000},"page":"53-56","source":"Crossref","is-referenced-by-count":1,"title":["Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system"],"prefix":"10.1109","author":[{"given":"Benjamin","family":"Devlin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Makoto","family":"Ikeda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kunihiro","family":"Asada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","first-page":"177","article-title":"Moebius Circuit: Dual-Rail Dynamic Logic for Logic Gate Level Pipeline with Error Gate Search Feature","author":"myeonggyu","year":"2009","journal-title":"VLSI 2009 Proceedings Nineteenth Great Lakes Symposium on"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/APEMC.2010.5475640"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/4.509871"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/LES.2010.2089428"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/TVLSI.2009.2014381"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1147\/rd.282.0124"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/TVLSI.2007.902206"},{"key":"7","doi-asserted-by":"crossref","first-page":"1110","DOI":"10.1109\/T-C.1969.222594","article-title":"design of asynchronous circuits assuming unbounded gate delays","volume":"c 18","author":"armstrong","year":"1969","journal-title":"IEEE Transactions on Computers"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/TC.1968.226879"},{"key":"5","doi-asserted-by":"crossref","first-page":"410","DOI":"10.1109\/TVLSI.2008.2011554","article-title":"Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits","volume":"18","author":"weidong","year":"2010","journal-title":"IEEE Trans Very Large Scale Integration (VLSI) Systems"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/TDSC.2008.37"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ASSCC.2010.5716572"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ESSCIRC.2009.5326010"}],"event":{"name":"2011 18th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2011)","start":{"date-parts":[[2011,12,11]]},"location":"Beirut, Lebanon","end":{"date-parts":[[2011,12,14]]}},"container-title":["2011 18th IEEE International Conference on Electronics, Circuits, and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6111681\/6122192\/06122212.pdf?arnumber=6122212","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T08:36:57Z","timestamp":1497947817000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6122212\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/icecs.2011.6122212","relation":{},"subject":[],"published":{"date-parts":[[2011,12]]}}}