{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T22:16:46Z","timestamp":1730240206052,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/icecs.2012.6463548","type":"proceedings-article","created":{"date-parts":[[2013,2,23]],"date-time":"2013-02-23T07:18:16Z","timestamp":1361603896000},"page":"877-880","source":"Crossref","is-referenced-by-count":7,"title":["Dedicated FPGA communication architecture and design for a large-scale neuromorphic system"],"prefix":"10.1109","author":[{"given":"V.","family":"Thanasoulis","sequence":"first","affiliation":[]},{"given":"J.","family":"Partzsch","sequence":"additional","affiliation":[]},{"given":"S.","family":"Hartmann","sequence":"additional","affiliation":[]},{"given":"C.","family":"Mayr","sequence":"additional","affiliation":[]},{"given":"R.","family":"Schuffny","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.302"},{"key":"11","article-title":"Design and implementation of a multi-class network architecture for hardware neural networks","author":"philipp","year":"2008","journal-title":"Uhei"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2005.1596997"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1152\/jn.00686.2005"},{"key":"2","first-page":"1947","author":"schemmel","year":"2010","journal-title":"A wafer-scale neuromorphic hardware system for large-scale neural modeling Iscas"},{"key":"1","article-title":"Spinnaker: A multi-core systemon-chip for massively-parallel neural net simulation","author":"painkras","year":"2012","journal-title":"CICC"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378041"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.17487\/rfc0768"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.17487\/rfc1122"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724670"},{"key":"4","first-page":"1642","article-title":"A VLSI Implementation of the adaptive exponential integrate-and-fire neuron model","volume":"23","author":"millner","year":"2010","journal-title":"Advances in neural information processing systems"},{"journal-title":"A serial communication infrastructure for multi-chip address event systems ISCAS","year":"2008","author":"fasnacht","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2009.2023653"}],"event":{"name":"2012 19th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2012)","start":{"date-parts":[[2012,12,9]]},"location":"Seville, Seville, Spain","end":{"date-parts":[[2012,12,12]]}},"container-title":["2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6450169\/6463499\/06463548.pdf?arnumber=6463548","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T17:21:29Z","timestamp":1490203289000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6463548\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/icecs.2012.6463548","relation":{},"subject":[],"published":{"date-parts":[[2012,12]]}}}