{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:38:01Z","timestamp":1729629481071,"version":"3.28.0"},"reference-count":32,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/icecs.2013.6815441","type":"proceedings-article","created":{"date-parts":[[2014,5,16]],"date-time":"2014-05-16T23:05:07Z","timestamp":1400281507000},"page":"409-412","source":"Crossref","is-referenced-by-count":2,"title":["Using body bias when upsizing length for maximizing the static noise margins of CMOS gates"],"prefix":"10.1109","author":[{"given":"Fekri","family":"Kharbash","sequence":"first","affiliation":[]},{"given":"Valeriu","family":"Beiu","sequence":"additional","affiliation":[]},{"given":"Mihai","family":"Tache","sequence":"additional","affiliation":[]},{"given":"Walid","family":"Ibrahim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","DOI":"10.1117\/12.774116","article-title":"Analysis of OPC optical model accuracy with detailed scanner information","author":"zavyalova","year":"2008","journal-title":"Proc SPIE 6924"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"18","doi-asserted-by":"crossref","first-page":"509","DOI":"10.1109\/TCAD.2011.2176123","article-title":"GREDA: A fast and more accurate CMOS gates reliability EDA tool","volume":"31","author":"ibrahim","year":"2012","journal-title":"IEEE Trans CAD"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.815862"},{"year":"0","key":"16"},{"key":"13","first-page":"1480","article-title":"Multiobjective optimization for transistor sizing of sub-threshold CMOS logic standard cells","author":"blesken","year":"2010","journal-title":"Proc ISCAS"},{"year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2112595"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493988"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1994.379721"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2012.2206249"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/4.245594"},{"key":"23","first-page":"76","article-title":"Ultra low power supply voltage (0. 3V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well","author":"shibata","year":"1998","journal-title":"Proc VLSI"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"25","first-page":"116","article-title":"A 9-W 50MHz 32b adder using a self-adjusted forward body bias in SoCs","author":"ishibashi","year":"2003","journal-title":"Proc ISSCC"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231824"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332641"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810054"},{"journal-title":"Body Effect and Body Biasing","year":"2012","key":"29"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1979.1051221"},{"key":"2","first-page":"16","article-title":"Noise margin and noise immunity in logic circuits","volume":"1","author":"hill","year":"1968","journal-title":"Microelectronics Journal"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2034233"},{"year":"0","key":"1"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2013.10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2006.882565"},{"key":"6","first-page":"327","article-title":"Selective gate-length biasing for cost-effective runtime leakage control","author":"gupta","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2158708"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523623"},{"key":"31","first-page":"160","article-title":"Impact of back bias on ultra-thin body and BOX (UTBB) devices","author":"liu","year":"2011","journal-title":"Proc VLSI"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/13.241612"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005413"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.911033"}],"event":{"name":"2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)","start":{"date-parts":[[2013,12,8]]},"location":"Abu Dhabi, United Arab Emirates","end":{"date-parts":[[2013,12,11]]}},"container-title":["2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6810206\/6815321\/06815441.pdf?arnumber=6815441","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T13:22:10Z","timestamp":1498137730000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6815441\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/icecs.2013.6815441","relation":{},"subject":[],"published":{"date-parts":[[2013,12]]}}}