{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T20:18:42Z","timestamp":1725394722579},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1109\/icecs.2014.7050001","type":"proceedings-article","created":{"date-parts":[[2015,3,3]],"date-time":"2015-03-03T20:03:03Z","timestamp":1425412983000},"page":"379-382","source":"Crossref","is-referenced-by-count":1,"title":["Distributed asynchronous controllers for clock management in low power systems"],"prefix":"10.1109","author":[{"given":"Chadi Al","family":"Khatib","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Claire","family":"Aupetit","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alexandre","family":"Chagoya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cyril","family":"Chevalier","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gilles","family":"Sicard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Laurent","family":"Fesquet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1998.666491"},{"key":"ref3","article-title":"Principles of asynchronous circuit design - A systems perspective","author":"sparse","year":"2001","journal-title":"Kluwer Academic Publishers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2002.996774"},{"key":"ref5","first-page":"79","article-title":"Logic Synthesis of Asynchronous Micropipeline Circuits","author":"rezzag","year":"2004","journal-title":"INP Grenoble"},{"key":"ref7","article-title":"Pipelined Asynchronous circuits","author":"lines","year":"1995","journal-title":"California Institute of Technology"},{"key":"ref2","first-page":"1","article-title":"Asynchronous Circuits Design: An Architectural Approach","author":"renaudin","year":"2003","journal-title":"V Escola deMicroeletrônica da SEC-Sul"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2159284"}],"event":{"name":"2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2014,12,7]]},"location":"Marseille, France","end":{"date-parts":[[2014,12,10]]}},"container-title":["2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7041007\/7049902\/07050001.pdf?arnumber=7050001","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:18:09Z","timestamp":1490383089000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7050001\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,12]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/icecs.2014.7050001","relation":{},"subject":[],"published":{"date-parts":[[2014,12]]}}}