{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,20]],"date-time":"2026-09-20T05:27:19Z","timestamp":1789882039093,"version":"4.0.1"},"reference-count":26,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/icecs.2015.7440264","type":"proceedings-article","created":{"date-parts":[[2016,3,29]],"date-time":"2016-03-29T20:53:22Z","timestamp":1459284802000},"page":"121-124","source":"Crossref","is-referenced-by-count":3,"title":["Process variability in FinFET standard cells with different transistor sizing techniques"],"prefix":"10.1109","author":[{"given":"Alexandra L.","family":"Zimpeck","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Cristina","family":"Meinhardt","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gracieli","family":"Posser","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Design for Success: USB IP for FinFET Process","author":"christiansen","year":"2015","journal-title":"DesignWare Technical Bulletin Synopsys"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537930"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229286"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.07.023"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131494"},{"key":"ref15","first-page":"67","article-title":"Sub 50-nm FinFET: PFET","author":"huang","year":"1999","journal-title":"Tech Digest IEDM"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229286"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71752-4"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2012.77"},{"key":"ref19","article-title":"FinFET standard cell optimization for performance and manufacturability. Thesis - University of Texas at Austin","author":"zhang","year":"2012"},{"key":"ref4","article-title":"Who Needs to Lead at the 14, 10 and 7nm nodes","author":"jones","year":"0"},{"key":"ref3","article-title":"International technology roadmap for semiconductors","year":"2011","journal-title":"ITRS"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2002.807392"},{"key":"ref5","article-title":"IBM Discloses Working Version of a Much Higher-Capacity Chip","author":"markoff","year":"0"},{"key":"ref8","article-title":"Performance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET devices","author":"posser","year":"2014","journal-title":"ISVLSI"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISDRS.2009.5378198"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/5.915374"},{"key":"ref9","article-title":"Logical Effort: designing fast cmos circuits","author":"sutherland","year":"1999","journal-title":"Morgan Kaufmann Publishers Inc"},{"key":"ref1","first-page":"207","article-title":"FinFETs for nanoscale cmos digital integrated circuits","author":"king","year":"2005","journal-title":"Int Conf Computer-Aided Design"},{"key":"ref20","author":"kleeberger","year":"2013","journal-title":"Predicting future product performance Modeling and evaluation of standard cells in FinFET technology Design Automation Conference (DAC)"},{"key":"ref22","article-title":"Thermal analysis of finfets and its application to gate sizing","author":"swahn","year":"2005","journal-title":"ACM\/IEEE International Workshop on Timing Issues"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488764"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2015.06.039"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2014.7050050"},{"key":"ref26","doi-asserted-by":"crossref","DOI":"10.1145\/2228360.2228414","article-title":"Explorating sub-20nm FinFET design with predictive technology models","author":"sinha","year":"2012","journal-title":"DAC"},{"key":"ref25","article-title":"Predictive Technology Models","year":"0","journal-title":"PTM"}],"event":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","location":"Cairo","start":{"date-parts":[[2015,12,6]]},"end":{"date-parts":[[2015,12,9]]}},"container-title":["2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7430153\/7440163\/07440264.pdf?arnumber=7440264","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,5]],"date-time":"2019-09-05T22:44:09Z","timestamp":1567723449000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7440264\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":26,"URL":"https:\/\/doi.org\/10.1109\/icecs.2015.7440264","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}