{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:49:49Z","timestamp":1767340189893},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,12]]},"DOI":"10.1109\/icecs.2015.7440279","type":"proceedings-article","created":{"date-parts":[[2016,3,30]],"date-time":"2016-03-30T00:53:22Z","timestamp":1459299202000},"page":"183-186","source":"Crossref","is-referenced-by-count":14,"title":["Performance evaluation of dynamic partial reconfiguration techniques for software defined radio implementation on FPGA"],"prefix":"10.1109","author":[{"given":"Amr","family":"Hassan","sequence":"first","affiliation":[]},{"given":"Ramy","family":"Ahmed","sequence":"additional","affiliation":[]},{"given":"Hassan","family":"Mostafa","sequence":"additional","affiliation":[]},{"given":"Hossam A. H.","family":"Fahmy","sequence":"additional","affiliation":[]},{"given":"Ahmed","family":"Hussien","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.2008.4526368"},{"key":"ref3","first-page":"253","article-title":"Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: A Case Study","author":"tan","year":"2006","journal-title":"Proceedings of ERSA'06"},{"journal-title":"Xilinx Inc","article-title":"Partial Reconfiguration User Guide (UG702)","year":"2013","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272463"},{"journal-title":"Xilinx Inc","article-title":"Virtex-5 FPGA Configuration User Guide (UGI91)","year":"2012","key":"ref11"},{"key":"ref5","article-title":"Managing Dynamic Partial Reconfiguration on Heterogeneous SDR Platforms","author":"delahaye","year":"2005","journal-title":"SDR Forum Technical Conference'05"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2068716.2068722"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2012.6412113"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311188"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2007.370362"},{"key":"ref1","article-title":"Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations","author":"liuzy","year":"2010","journal-title":"ReCoSoC"}],"event":{"name":"2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","start":{"date-parts":[[2015,12,6]]},"location":"Cairo, Egypt","end":{"date-parts":[[2015,12,9]]}},"container-title":["2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7430153\/7440163\/07440279.pdf?arnumber=7440279","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T11:53:19Z","timestamp":1490097199000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7440279\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,12]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/icecs.2015.7440279","relation":{},"subject":[],"published":{"date-parts":[[2015,12]]}}}