{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,5]],"date-time":"2026-01-05T07:13:59Z","timestamp":1767597239147,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,12]]},"DOI":"10.1109\/icecs.2016.7841255","type":"proceedings-article","created":{"date-parts":[[2017,2,7]],"date-time":"2017-02-07T15:56:21Z","timestamp":1486482981000},"page":"528-531","source":"Crossref","is-referenced-by-count":8,"title":["PVT variability analysis of FinFET and CMOS XOR circuits at 16nm"],"prefix":"10.1109","author":[{"given":"Fabio G. R. G.","family":"da Silva","sequence":"first","affiliation":[]},{"given":"Paulo F.","family":"Butzen","sequence":"additional","affiliation":[]},{"given":"Cristina","family":"Meinhardt","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"1","article-title":"Subthreshold 1-bit Full Adder in 100nm Technologies","author":"moalemi","year":"2007","journal-title":"ISVLSI"},{"key":"ref11","article-title":"A High Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates","author":"chowdhury","year":"2008","journal-title":"World Academy of Science Engineering and Technology"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488775"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2014.07.023"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/82.996055","article-title":"Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR-XNOR Gates","volume":"49","author":"bui","year":"2002","journal-title":"IEEE Trans on Circuits and Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523687"},{"key":"ref6","article-title":"A Comparative Performance Analysis of Various CMOS Design Techniques for XOR and XNOR Circuits","author":"mishra","year":"2010","journal-title":"Journal of Emerging Technologies"},{"key":"ref5","first-page":"25","article-title":"New 4-Transistor XOR and XNOR Designs","author":"bui","year":"2000","journal-title":"Proc IEEE Asia-Pacific Conf ASICs"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/5.915374"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672005"},{"key":"ref2","first-page":"708","article-title":"New Efficient Designs for XOR and XNOR Functions on the Transistor Lever","volume":"29","author":"wang","year":"1994","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCCT.2011.6075163"},{"key":"ref9","first-page":"207","article-title":"FinFETs for nanoscale CMOS digital integrated circuits","author":"king","year":"2005","journal-title":"Proc Int Conf Computer-Aided Design"}],"event":{"name":"2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2016,12,11]]},"location":"Monte Carlo, Monaco","end":{"date-parts":[[2016,12,14]]}},"container-title":["2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7829200\/7841114\/07841255.pdf?arnumber=7841255","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,18]],"date-time":"2019-09-18T07:12:03Z","timestamp":1568790723000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7841255\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,12]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/icecs.2016.7841255","relation":{},"subject":[],"published":{"date-parts":[[2016,12]]}}}