{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T22:20:48Z","timestamp":1730240448735,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/icecs.2018.8617849","type":"proceedings-article","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T05:16:09Z","timestamp":1548306969000},"page":"429-432","source":"Crossref","is-referenced-by-count":0,"title":["A Novel Sizing Method Aiming Security Against Differential Power Analysis"],"prefix":"10.1109","author":[{"given":"Vitor G.","family":"Lima","sequence":"first","affiliation":[]},{"given":"Plinio","family":"Finkenauer","sequence":"additional","affiliation":[]},{"given":"Vinicius V.","family":"Camargo","sequence":"additional","affiliation":[]},{"given":"Felipe S.","family":"Marques","sequence":"additional","affiliation":[]},{"given":"Leomar R.","family":"Junior","sequence":"additional","affiliation":[]},{"given":"Rafael I.","family":"Soares","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2007.4402510"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1049\/el.2014.1559"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2752212"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCEET.2012.6203865"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2013.04.003"},{"key":"ref15","article-title":"A Flip-Flop Implementation for the DPA-Resistant Delay-Based Dual-Rail Pre-Charge Logic Family","author":"bongiovanni","year":"2013","journal-title":"Mix Des Int Circ Systems (MIXDES)"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"},{"key":"ref17","volume":"31","author":"mangard","year":"2008","journal-title":"Power Analysis Attacks Revealing the Secrets of Smart Cards"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s11081-012-9208-0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SSCI.2015.46"},{"key":"ref6","article-title":"A Linear Programming Formulation for Security-Aware Gate Sizing","author":"bhattacharya","year":"2008","journal-title":"Proceedings Great Lakes Symposium on VLSI GLSV"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.08.003"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2015.7285109"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629977"},{"key":"ref2","first-page":"388","article-title":"Differential Power Analysis","author":"kocher","year":"1999","journal-title":"19th An Int Conf on Adv in Cryptology"},{"key":"ref1","first-page":"125","article-title":"Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology","author":"kris","year":"2003","journal-title":"Int Work on Crypt Hard and Emb Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2015.7517071"}],"event":{"name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2018,12,9]]},"location":"Bordeaux","end":{"date-parts":[[2018,12,12]]}},"container-title":["2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8599658\/8617837\/08617849.pdf?arnumber=8617849","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T23:37:03Z","timestamp":1598225823000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8617849\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/icecs.2018.8617849","relation":{},"subject":[],"published":{"date-parts":[[2018,12]]}}}