{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:37:33Z","timestamp":1767339453878,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/icecs.2018.8617948","type":"proceedings-article","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T05:16:09Z","timestamp":1548306969000},"page":"717-720","source":"Crossref","is-referenced-by-count":14,"title":["A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay Lines"],"prefix":"10.1109","author":[{"given":"Nico","family":"Angeli","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Klaus","family":"Hofmann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2005.846307"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2348311"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2801030"},{"key":"ref13","first-page":"2700","article-title":"A 0.94-ps-rms-jitter 0.016-mm2 2.5-ghz multiphase generator pll with 360 digitally programmable phase shift for 10-gb\/s serial links","volume":"410","author":"toifl","year":"2005","journal-title":"JSSC"},{"key":"ref14","first-page":"627","article-title":"A wideband 3.6 ghz digital $\\delta\\sigma$ fractional-n pll with phase interpolation divider and digital spur cancellation","volume":"46","author":"zanuso","year":"2011","journal-title":"JSSC"},{"key":"ref4","first-page":"2338","article-title":"A 2.5 ghz all-digital delay-locked loop in $0.13 \\mu \\mathrm{m}$ cmos technology","volume":"42","author":"yang","year":"2007","journal-title":"JSSC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.874353"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2178557"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2028919"},{"key":"ref8","first-page":"3184","article-title":"A 2.4-ghz 2040-mhz channel wlan digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm cmos","volume":"47","author":"ravi","year":"2012","journal-title":"JSSC"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1049\/el:20081833"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858375"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"434","DOI":"10.1186\/s40064-016-2090-z","article-title":"A review on high-resolution cmos delay lines: towards sub-picosecond jitter performance","volume":"5","author":"abdulrazzaq","year":"2016","journal-title":"SpringerPlus"},{"key":"ref9","article-title":"A robust digital delay line architecture in a 0.13m cmos technology node for reduced design and process sensitivities","author":"raha","year":"2002","journal-title":"ISQED"}],"event":{"name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2018,12,9]]},"location":"Bordeaux","end":{"date-parts":[[2018,12,12]]}},"container-title":["2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8599658\/8617837\/08617948.pdf?arnumber=8617948","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T04:18:50Z","timestamp":1598242730000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8617948\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/icecs.2018.8617948","relation":{},"subject":[],"published":{"date-parts":[[2018,12]]}}}