{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T15:32:57Z","timestamp":1762011177294,"version":"build-2065373602"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,12]]},"DOI":"10.1109\/icecs.2018.8618062","type":"proceedings-article","created":{"date-parts":[[2019,1,24]],"date-time":"2019-01-24T05:16:09Z","timestamp":1548306969000},"page":"841-844","source":"Crossref","is-referenced-by-count":5,"title":["Can Approximate Computing Reduce Power Consumption on FPGAs?"],"prefix":"10.1109","author":[{"given":"Jorge","family":"Echavarria","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Katja","family":"Schutz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas","family":"Becher","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Wildermann","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jurgen","family":"Teich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.25"},{"key":"ref3","first-page":"1","article-title":"A low-power, high-performance approximate multiplier with configurable partial error recovery","author":"liu","year":"2014","journal-title":"2014 Design Automation and Test in Europe Conference and Exhibition"},{"key":"ref10","first-page":"85","article-title":"Multiplication of many-digital numbers by automatic computers","volume":"145","author":"karatsuba","year":"1962","journal-title":"Doklady Akad Nauk SSSR"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6388-8"},{"journal-title":"Digitale Hardware\/Software-Systeme Synthese und Optimierung","year":"2007","author":"teich","key":"ref11"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056832"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2520979"},{"key":"ref7","first-page":"7","article-title":"Efficient switching activity reduction technique for fault tolerant data bus","volume":"36","author":"sathish","year":"2011","journal-title":"International Journal of Computer Applications"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2016.7929536"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2027626"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"2003","author":"rabaey","key":"ref1"}],"event":{"name":"2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2018,12,9]]},"location":"Bordeaux","end":{"date-parts":[[2018,12,12]]}},"container-title":["2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8599658\/8617837\/08618062.pdf?arnumber=8618062","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T23:03:08Z","timestamp":1598223788000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8618062\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/icecs.2018.8618062","relation":{},"subject":[],"published":{"date-parts":[[2018,12]]}}}