{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T22:23:31Z","timestamp":1730240611034,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/icecs46596.2019.8964954","type":"proceedings-article","created":{"date-parts":[[2020,1,24]],"date-time":"2020-01-24T03:15:31Z","timestamp":1579835731000},"page":"634-637","source":"Crossref","is-referenced-by-count":0,"title":["Synthesizing Efficient Hardware from High-Level Functional Hardware Description Languages"],"prefix":"10.1109","author":[{"given":"Mahshid","family":"Shahmohammadian","sequence":"first","affiliation":[]},{"given":"Geoffrey","family":"Mainland","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Hardware design and implementation of the Schmidl-Cox synchronization algorithm for an OFDM transceiver","year":"2015","author":"morris","key":"ref10"},{"journal-title":"7 Series FPGAs Configurable Logic Block User Guide","first-page":"74","year":"2016","key":"ref11"},{"journal-title":"&#x201C;Setup and Hold Time&#x201D; Static Timing Analysis (STA) basic (Part 3a)","year":"0","author":"expert","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694368"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3110263"},{"key":"ref4","first-page":"1135","article-title":"Hardware Design and Functional Programming: a Perfect Match","volume":"11","author":"sheeran","year":"2005","journal-title":"J UCS"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/289423.289440"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/11560548_4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30494-4_2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC.2014.7040969"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-92995-6"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/359576.359579"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/800055.802026"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/26.650240"}],"event":{"name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2019,11,27]]},"location":"Genoa, Italy","end":{"date-parts":[[2019,11,29]]}},"container-title":["2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8955687\/8964633\/08964954.pdf?arnumber=8964954","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,19]],"date-time":"2022-07-19T20:24:44Z","timestamp":1658262284000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8964954\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/icecs46596.2019.8964954","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}