{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,21]],"date-time":"2025-08-21T18:43:17Z","timestamp":1755801797610,"version":"3.44.0"},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/icecs46596.2019.8965077","type":"proceedings-article","created":{"date-parts":[[2020,1,23]],"date-time":"2020-01-23T22:15:31Z","timestamp":1579817731000},"page":"482-485","source":"Crossref","is-referenced-by-count":4,"title":["A 12 GHz All-Digital PLL with linearized chirps for FMCW Radar"],"prefix":"10.1109","author":[{"given":"Markus","family":"Kempf","sequence":"first","affiliation":[{"name":"Eesy-ic GmbH,Analog design,Erlangen,Germany"}]},{"given":"Juergen","family":"Roeber","sequence":"additional","affiliation":[{"name":"Eesy-ic GmbH,Analog design,Erlangen,Germany"}]},{"given":"Frank","family":"Ohnhaeuser","sequence":"additional","affiliation":[{"name":"Eesy-ic GmbH,Erlangen,Germany"}]},{"given":"Robert","family":"Weigel","sequence":"additional","affiliation":[{"name":"Institute of technical electronics, University of Erlangen-Nuremberg,Erlangen,Germany"}]}],"member":"263","reference":[{"key":"ref4","article-title":"A 940 MHz-bandwidth 28.8 µs-period 8.9 GHz chirp frequency synthesizer pll in 65 nm cmos for x-band fmcw radar applications","author":"yeo","year":"0","journal-title":"IEEE International Solid-State Circuits Conference Session 7"},{"key":"ref3","article-title":"A 36.3-to-38.2 GHz ?216 dBc\/Hz 40nm cmos fractional-n fmcw chirp synthesizer pll with a continuous-time bandpass delta-sigma time-to-digital converter","author":"weyer","year":"0","journal-title":"IEEE International Solid-State Circuits Conference Session 7"},{"key":"ref6","article-title":"A 23 GHz low-phase-noise digital bang-bang pll for fast triangular and saw-tooth chirp modulation","author":"cherniak","year":"0","journal-title":"IEEE International Solid-State Circuits Conference Session 7"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/RFIC.2016.7508244"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/CECNet.2012.6201657"},{"key":"ref7","article-title":"An 82-to-108 GHz ?181 dB-FOM adpll employing a dco with split-transformer and dual-path switched-capacitor ladder and a clock-skew-sampling delta-sigma tdc","author":"huang","year":"0","journal-title":"IEEE International Solid-State Circuits Conference Session 7"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1002\/0470041951"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/JSSC.2014.2301764"}],"event":{"name":"2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2019,11,27]]},"location":"Genoa, Italy","end":{"date-parts":[[2019,11,29]]}},"container-title":["2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8955687\/8964633\/08965077.pdf?arnumber=8965077","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,20]],"date-time":"2025-08-20T18:35:08Z","timestamp":1755714908000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8965077\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/icecs46596.2019.8965077","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}