{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T01:30:01Z","timestamp":1725586201973},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,11,23]],"date-time":"2020-11-23T00:00:00Z","timestamp":1606089600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,11,23]],"date-time":"2020-11-23T00:00:00Z","timestamp":1606089600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,11,23]],"date-time":"2020-11-23T00:00:00Z","timestamp":1606089600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,11,23]]},"DOI":"10.1109\/icecs49266.2020.9294850","type":"proceedings-article","created":{"date-parts":[[2020,12,28]],"date-time":"2020-12-28T20:52:44Z","timestamp":1609188764000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs"],"prefix":"10.1109","author":[{"given":"Fanny","family":"Spagnolo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Fabio","family":"Frustaci","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefania","family":"Perri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pasquale","family":"Corsonello","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2004.10.004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.image.2018.07.007"},{"key":"ref10","article-title":"A 8-bit Dot-Product Acceleration","author":"fu","year":"2017","journal-title":"Xilinx White Paper (WP487 v 1 0)"},{"journal-title":"7 Series DSP48E1 Slice User Guide UG479 (V1 10)","year":"0","key":"ref6"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2018.8618010"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2913958"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2824280"},{"journal-title":"Variable Precision DSP Blocks in Cyclone V Devices","year":"0","key":"ref8"},{"journal-title":"UltraScale Architecture DSP Slice User Guide UG579 (v1 9)","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/s11554-017-0712-5"},{"journal-title":"Intel&#x00AE; Arria&#x00AE; 10 Native Fixed Point DSP IP Core User Guide UG-01163","year":"0","key":"ref9"},{"key":"ref1","first-page":"1","article-title":"IoT-based 3D convolution for video salient object detection","author":"dong","year":"2019","journal-title":"Neural Comput & Appl"}],"event":{"name":"2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2020,11,23]]},"location":"Glasgow, UK","end":{"date-parts":[[2020,11,25]]}},"container-title":["2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9294155\/9294779\/09294850.pdf?arnumber=9294850","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,28]],"date-time":"2022-06-28T00:07:52Z","timestamp":1656374872000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9294850\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,11,23]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icecs49266.2020.9294850","relation":{},"subject":[],"published":{"date-parts":[[2020,11,23]]}}}