{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T01:49:57Z","timestamp":1740102597581,"version":"3.37.3"},"reference-count":10,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,12,4]],"date-time":"2023-12-04T00:00:00Z","timestamp":1701648000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,12,4]],"date-time":"2023-12-04T00:00:00Z","timestamp":1701648000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100018693","name":"Horizon Europe","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100018693","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,12,4]]},"DOI":"10.1109\/icecs58634.2023.10382925","type":"proceedings-article","created":{"date-parts":[[2024,1,10]],"date-time":"2024-01-10T19:38:25Z","timestamp":1704915505000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS"],"prefix":"10.1109","author":[{"given":"Samuel","family":"Riedel","sequence":"first","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]},{"given":"Matheus","family":"Cavalcante","sequence":"additional","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]},{"given":"Manos","family":"Frouzakis","sequence":"additional","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]},{"given":"Domenic","family":"W\u00fcthrich","sequence":"additional","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]},{"given":"Enis","family":"Mustafa","sequence":"additional","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]},{"given":"Arlind","family":"Billa","sequence":"additional","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]},{"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"IIS, ETH Z&#x00FC;rich"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3307796"},{"volume-title":"Computer Architecture: A Quantitative Approach","year":"2017","author":"Hennessy","key":"ref2"},{"volume-title":"AI-deck 1.1 \u2013 Bitcraze store","year":"2023","key":"ref3"},{"article-title":"NVIDIA H100 tensor core GPU architecture","volume-title":"NVIDIA Corp., Tech. Rep.","year":"2022","key":"ref4"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3027900"},{"key":"ref6","article-title":"ISA extensions in the Snitch processor for signal processing","volume-title":"Politecnico di Torino, Tech. Rep.","author":"Mazzola","year":"2021"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC53450.2021.9567755"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3114881"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2018.8494247"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC55480.2022.9911384"}],"event":{"name":"2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)","start":{"date-parts":[[2023,12,4]]},"location":"Istanbul, Turkiye","end":{"date-parts":[[2023,12,7]]}},"container-title":["2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10382705\/10382711\/10382925.pdf?arnumber=10382925","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,13]],"date-time":"2024-01-13T18:25:05Z","timestamp":1705170305000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10382925\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,12,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/icecs58634.2023.10382925","relation":{},"subject":[],"published":{"date-parts":[[2023,12,4]]}}}