{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,11]],"date-time":"2026-02-11T01:04:30Z","timestamp":1770771870407,"version":"3.50.0"},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T00:00:00Z","timestamp":1763337600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,11,17]],"date-time":"2025-11-17T00:00:00Z","timestamp":1763337600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,11,17]]},"DOI":"10.1109\/icecs66544.2025.11270800","type":"proceedings-article","created":{"date-parts":[[2025,12,9]],"date-time":"2025-12-09T18:31:34Z","timestamp":1765305094000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["A Memoryless Stream Processing Architecture for Energy-Efficient Signal Processing"],"prefix":"10.1109","author":[{"given":"Clara","family":"Ciocan","sequence":"first","affiliation":[{"name":"Universit&#x00E9; Paris-Saclay,CEA, CNRS, SPEC,France"}]},{"given":"Anthony","family":"Kolar","sequence":"additional","affiliation":[{"name":"Universit&#x00E9; Paris-Saclay,CentraleSup&#x00E9;lec, CNRS, GEEPS,France"}]},{"given":"Mathieu","family":"Thevenin","sequence":"additional","affiliation":[{"name":"Universit&#x00E9; Paris-Saclay,CEA, CNRS, SPEC,France"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757323"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.21236\/ADA605735"},{"key":"ref3","author":"Hennessy","year":"2019","journal-title":"Computer Architecture: A Quantitative Approach"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.881821"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2002.1106783"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s11554-018-0808-6"},{"key":"ref8","volume-title":"NVIDIA Ampere Architecture In-Depth","year":"2020"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/r10-htc54060.2022.9929533"},{"key":"ref10","volume-title":"Cadence digital full flow: Xcelium, genus, innovus"},{"key":"ref11","volume-title":"RISC-V Formal Verification Framework","year":"2023"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/access.2022.3174125"}],"event":{"name":"2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)","location":"Marrakech, Morocco","start":{"date-parts":[[2025,11,17]]},"end":{"date-parts":[[2025,11,19]]}},"container-title":["2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11270487\/11270494\/11270800.pdf?arnumber=11270800","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,10]],"date-time":"2026-02-10T20:59:07Z","timestamp":1770757147000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11270800\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,17]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icecs66544.2025.11270800","relation":{},"subject":[],"published":{"date-parts":[[2025,11,17]]}}}