{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T15:52:22Z","timestamp":1762876342531,"version":"3.37.3"},"reference-count":36,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,12,6]],"date-time":"2021-12-06T00:00:00Z","timestamp":1638748800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,6]],"date-time":"2021-12-06T00:00:00Z","timestamp":1638748800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,6]],"date-time":"2021-12-06T00:00:00Z","timestamp":1638748800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100002347","name":"BMBF","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100002347","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,12,6]]},"DOI":"10.1109\/icfpt52863.2021.9609930","type":"proceedings-article","created":{"date-parts":[[2021,11,23]],"date-time":"2021-11-23T21:47:48Z","timestamp":1637704068000},"page":"1-9","source":"Crossref","is-referenced-by-count":8,"title":["FLOWER: A comprehensive dataflow compiler for high-level synthesis"],"prefix":"10.1109","author":[{"given":"Puya","family":"Amiri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arsene","family":"Perard-Gayot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Richard","family":"Membarth","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philipp","family":"Slusallek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roland","family":"Leiba","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sebastian","family":"Hack","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174248"},{"key":"ref32","article-title":"StencilFlow: Mapping large stencil programs to distributed spatial computing systems","author":"de fine licht","year":"2020","journal-title":"CoRR"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref30","article-title":"High level synthesis with a dataflow architectural template","author":"cheng","year":"2016","journal-title":"CoRR"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3295500.3356173"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/3289602.3293907"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICDCS.2019.00180"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2897824.2925892"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2394802"},{"key":"ref12","first-page":"1026","article-title":"Generating FPGA-based Image Processing Accelerators with Hipacc","author":"reiche","year":"2017","journal-title":"Proceedings of the International Conference on Computer Aided Design (ICCAD)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375296"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_65"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3180481"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3192366.3192379"},{"key":"ref17","first-page":"1","article-title":"Dataflow\/Actor-Oriented language for the design of complex signal processing systems","author":"lucarz","year":"2008","journal-title":"Conference on Design and Architectures for Signal and Image Processing (DASIP 2008)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3315454.3329957"},{"key":"ref28","first-page":"1","article-title":"A unified backend for targeting FPGAs from DSLs","author":"sozzo","year":"2018","journal-title":"IEEE 29th International Conference on Application-specific Systems Architectures and Processors (ASAP)"},{"key":"ref4","first-page":"3202","article-title":"AnyHLS: High-level synthesis with partial evaluation","volume":"39","author":"\u00f6zkan","year":"2020","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) (Proceedings of CODES+ISSS 2020)"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2018.00023"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/H2RC49586.2019.00006"},{"key":"ref6","article-title":"Best-effort FPGA programming: A few steps can go a long way","volume":"abs 1807 1340","author":"cong","year":"2018","journal-title":"CoRR"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2019.00036"},{"key":"ref5","first-page":"119:1","article-title":"AnyDSL: A partial evaluation framework for programming high-performance libraries","volume":"2","author":"lei\u00dfa","year":"2018","journal-title":"Proceedings of the ACM on Programming Languages (PACMPL)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2967938.2967969"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375320"},{"key":"ref2","first-page":"1","article-title":"Invited tutorial: OpenCL design flows for intel and xilinx FPGAs: Using common design patterns and dealing with vendor-specific differences","author":"kenter","year":"0","journal-title":"Sixth International Workshop on FPGAs for Software Programmers (FSP Workshop)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3377555.3377899"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.3039409"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2601097.2601174"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2514740"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.69"},{"key":"ref24","first-page":"202","article-title":"A graph-based higher-order intermediate representation","author":"lei\u00dfa","year":"2015","journal-title":"3rd IEEE\/ACM International Symposium on Code generation and optimization (CGO"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2934583.2953984"},{"key":"ref26","first-page":"393","article-title":"Predictable accelerator design with timesensitive affine types","author":"nigam","year":"0","journal-title":"Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1023\/A:1010095604496"}],"event":{"name":"2021 International Conference on Field-Programmable Technology (ICFPT)","start":{"date-parts":[[2021,12,6]]},"location":"Auckland, New Zealand","end":{"date-parts":[[2021,12,10]]}},"container-title":["2021 International Conference on Field-Programmable Technology (ICFPT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9609797\/9609698\/09609930.pdf?arnumber=9609930","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:51:55Z","timestamp":1652201515000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9609930\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12,6]]},"references-count":36,"URL":"https:\/\/doi.org\/10.1109\/icfpt52863.2021.9609930","relation":{},"subject":[],"published":{"date-parts":[[2021,12,6]]}}}