{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:18:13Z","timestamp":1729628293695,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1109\/icicdt.2013.6563341","type":"proceedings-article","created":{"date-parts":[[2013,8,14]],"date-time":"2013-08-14T16:20:40Z","timestamp":1376497240000},"page":"223-226","source":"Crossref","is-referenced-by-count":1,"title":["TSV count minimization and thermal analysis for 3D Tree-based FPGA"],"prefix":"10.1109","author":[{"given":"Vinod","family":"Pangracious","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Habib","family":"Mehrez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zied","family":"Marakchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","first-page":"90","author":"ayala","year":"2009","journal-title":"Through Silicon Via-Based Grid for Thermal Control in 3D Chips"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2007.373897"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAPT.2002.808011"},{"journal-title":"Monitoring Temperature in FPGA Based SoCs International Conference on Computer Aided Design (ICCAD)","year":"2005","author":"velusamy","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/92.902261"},{"key":"2","article-title":"Reconfigurable architectures for General-Purpose computing","author":"dehon","year":"1996","journal-title":"Ph D Dissertation Department of Elect Engg and Computer Science"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2742-8"},{"key":"10","first-page":"520531","volume":"22","author":"ababei","year":"2005","journal-title":"Placement and Routing in 3D Integrated Circuits IEEE Design & Test of Computers"},{"year":"0","key":"7","first-page":"17"},{"journal-title":"Techniques for Producing 3D ICs with High-Density Interconnect Tezzaron Semiconductor Naperville IL","year":"2005","author":"gupta","key":"6"},{"key":"5","first-page":"197","author":"pangracious","year":"2013","journal-title":"Performance Analysis and Optimization of High Density Tree-based 3D Multilevel FPGA"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1572471.1572486"},{"key":"9","doi-asserted-by":"crossref","DOI":"10.1155\/2008\/764942","article-title":"Architecture level exploration of alternative schmes targeting 3D FPGAs","author":"siozios","year":"2008","journal-title":"A Software Supported Methodology International Journal of Reconfigurable Computing"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/259837"}],"event":{"name":"2013 International Conference on IC Design & Technology (ICICDT)","start":{"date-parts":[[2013,5,29]]},"location":"Pavia, Italy","end":{"date-parts":[[2013,5,31]]}},"container-title":["Proceedings of 2013 International Conference on IC Design &amp; Technology (ICICDT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6556112\/6563281\/06563341.pdf?arnumber=6563341","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T17:50:29Z","timestamp":1498067429000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6563341\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/icicdt.2013.6563341","relation":{},"subject":[],"published":{"date-parts":[[2013,5]]}}}