{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,12]],"date-time":"2026-02-12T12:35:37Z","timestamp":1770899737460,"version":"3.50.1"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/icicdt.2014.6838582","type":"proceedings-article","created":{"date-parts":[[2014,7,28]],"date-time":"2014-07-28T15:03:50Z","timestamp":1406559830000},"page":"1-4","source":"Crossref","is-referenced-by-count":9,"title":["Thermal-driven 3D floorplanning using localized TSV placement"],"prefix":"10.1109","author":[{"given":"Puskar","family":"Budhathoki","sequence":"first","affiliation":[]},{"given":"Andreas","family":"Henschel","sequence":"additional","affiliation":[]},{"given":"Ibrahim Abe M.","family":"Elfadel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1021\/ma902122u"},{"key":"16","year":"2000"},{"key":"13","year":"2011"},{"key":"14","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/DATE.2006.243773","article-title":"3D floorplanning with thermal vias","author":"wong","year":"2006","journal-title":"Design Automation and Test in Europe 2006 DATE'06 Proceedings IEEE"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"12","first-page":"19","article-title":"Fast thermal analysis of vertically integrated circuits (3d ics) using power blurring method","volume":"9","author":"park","year":"2009","journal-title":"InterPACK"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/92.974905"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2006.1648629"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228477"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/STHERM.1992.172851"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055171"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796518"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2002.1014915"},{"key":"9","author":"knechtel","year":"0","journal-title":"Structural Planning of 3DIC Interconnects by Block Alignment"},{"key":"8","first-page":"962","article-title":"Integration of thermal management and floorplanning based on threedimensional layout representations","author":"budhathoki","year":"2013","journal-title":"Proc IEEE Int Conf Electronics Circuits and Systems"}],"event":{"name":"2014 IEEE International Conference on IC Design & Technology (ICICDT)","location":"Austin, TX, USA","start":{"date-parts":[[2014,5,28]]},"end":{"date-parts":[[2014,5,30]]}},"container-title":["2014 IEEE International Conference on IC Design &amp; Technology"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6832295\/6838579\/06838582.pdf?arnumber=6838582","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T13:25:58Z","timestamp":1498137958000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6838582\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/icicdt.2014.6838582","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}